Programming the Basic Computer MCQ Questions and Answers
1. The component responsible for decoding the operation code in a basic computer is:
A) Memory Address Register
B) Control Unit
C) Program Counter
D) Arithmetic Logic Unit
Answer: B) Control Unit
2. In machine language, each instruction is represented by:
A) Mnemonics and labels
B) Binary code specific to CPU architecture
C) ASCII characters
D) Hexadecimal constants only
Answer: B) Binary code specific to CPU architecture
3. Which of the following operations is not typically part of the instruction cycle?
A) Fetch
B) Decode
C) Assemble
D) Execute
Answer: C) Assemble
4. The instruction ADD M means:
A) Add content of accumulator to memory
B) Add memory address to program counter
C) Add content of memory M to accumulator
D) Add instruction counter to memory
Answer: C) Add content of memory M to accumulator
5. The “effective address” in instruction execution refers to:
A) The opcode address
B) The actual memory address of the operand
C) The address of next instruction
D) The address of the instruction register
Answer: B) The actual memory address of the operand
6. If a basic computer has 12-bit instructions and 4-bit opcodes, how many distinct instructions can exist?
A) 8
B) 12
C) 16
D) 32
Answer: C) 16
7. The Memory Reference Instruction in a basic computer requires:
A) No memory access
B) Access to main memory for operand fetching
C) Use of immediate data
D) Use of interrupt
Answer: B) Access to main memory for operand fetching
8. In a simple machine, the instruction CLA means:
A) Clear memory address
B) Clear accumulator
C) Clear control flag
D) Clear arithmetic unit
Answer: B) Clear accumulator
9. Micro-operations are:
A) High-level operations performed by compiler
B) Elementary hardware-level operations executed in one clock cycle
C) Software-level subroutines
D) Input-output routines
Answer: B) Elementary hardware-level operations executed in one clock cycle
10. The “Fetch-Decode-Execute” cycle is controlled by:
A) ALU only
B) Timing and control unit
C) Data bus
D) Program Counter
Answer: B) Timing and control unit
11. An assembly language instruction that represents a single machine instruction is called:
A) Macro
B) Mnemonic
C) Operand
D) Directive
Answer: B) Mnemonic
12. A label in assembly programming is used to:
A) Represent an opcode
B) Store binary data
C) Mark a memory address or jump target
D) Reserve registers
Answer: C) Mark a memory address or jump target
13. The assembler translates assembly code into:
A) Object code
B) Machine code
C) Binary instructions
D) All of the above
Answer: D) All of the above
14. Which of the following is not a function of an assembler?
A) Symbol resolution
B) Opcode translation
C) Instruction execution
D) Memory allocation
Answer: C) Instruction execution
15. A pseudo-op in assembly is:
A) An instruction that directs the assembler but does not generate machine code
B) A real hardware operation
C) A subroutine call
D) A register alias
Answer: A) An instruction that directs the assembler but does not generate machine code
16. The directive END in assembly indicates:
A) The end of memory
B) The end of an instruction
C) The end of the source program
D) End of a subroutine
Answer: C) The end of the source program
17. Which of the following cannot be a label in assembly language?
A) START
B) LOOP
C) MOV
D) NEXT
Answer: C) MOV
18. The “two-pass assembler” performs symbol resolution in:
A) The second pass
B) The first pass
C) Both passes
D) Post-processing stage
Answer: B) The first pass
19. A forward reference in assembly language occurs when:
A) A symbol is defined before use
B) A symbol is used before being defined
C) A label is declared twice
D) The assembler makes a syntax error
Answer: B) A symbol is used before being defined
20. The output file of an assembler is called:
A) Source file
B) Object file
C) Listing file
D) Machine directive
Answer: B) Object file
Assembler and Symbol Table
21. The symbol table in an assembler is used for:
A) Operand execution
B) Data storage
C) Mapping symbolic names to addresses
D) Debugging
Answer: C) Mapping symbolic names to addresses
22. Relocation in assembly means:
A) Changing data segment
B) Adjusting addresses when program is loaded to a new memory location
C) Moving subroutines
D) Modifying mnemonics
Answer: B) Adjusting addresses when program is loaded to a new memory location
23. Literal pools in assembly refer to:
A) Constants stored in memory for use by instructions
B) Data buffers
C) Instruction queues
D) Registers
Answer: A) Constants stored in memory for use by instructions
24. A macro differs from a subroutine in that:
A) Macros are stored in memory
B) Subroutines execute faster
C) Macros are expanded inline at assembly time
D) Subroutines require no return address
Answer: C) Macros are expanded inline at assembly time
25. During Pass 2 of assembly, the assembler:
A) Builds the symbol table
B) Generates machine code using the symbol table
C) Defines macros
D) Collects pseudo-ops
Answer: B) Generates machine code using the symbol table
26. The loop control instruction ISZ works by:
A) Incrementing accumulator
B) Incrementing memory and skipping next instruction if zero
C) Decrementing PC
D) Incrementing instruction register
Answer: B) Incrementing memory and skipping next instruction if zero
27. The main purpose of a loop counter register is to:
A) Hold intermediate arithmetic results
B) Keep track of iterations
C) Manage flags
D) Store program code
Answer: B) Keep track of iterations
28. A conditional branch instruction changes program flow based on:
A) Clock pulses
B) Data type
C) Status flags
D) Opcode value
Answer: C) Status flags
29. In assembly, JMP LABEL indicates:
A) Jump if accumulator is zero
B) Unconditional jump to LABEL
C) Jump based on flag
D) Jump and store
Answer: B) Unconditional jump to LABEL
30. A loop that never terminates is caused by:
A) Stack overflow
B) Incorrect exit condition
C) Zero flag reset
D) Addressing error
Answer: B) Incorrect exit condition
31. When a subroutine is called, the CPU typically:
A) Pushes the return address to the stack
B) Stores the return address in accumulator
C) Overwrites program counter permanently
D) Saves current instruction in memory
Answer: A) Pushes the return address to the stack
32. The instruction CALL SUBR performs which operation first?
A) Loads accumulator
B) Stores next instruction address before jumping
C) Clears flags
D) Pushes opcode to stack
Answer: B) Stores next instruction address before jumping
33. During a subroutine return, the CPU usually:
A) Pops the top of stack into accumulator
B) Pops the top of stack into program counter
C) Clears the memory buffer
D) Reloads opcode
Answer: B) Pops the top of stack into program counter
34. Stack overflow occurs when:
A) Stack pointer is uninitialized
B) Stack grows upward
C) Stack pointer exceeds its maximum limit
D) Stack pointer becomes negative
Answer: C) Stack pointer exceeds its maximum limit
35. Stack memory is used for:
A) I/O buffering
B) Opcode storage
C) Temporary storage of return addresses and local data
D) Symbol mapping
Answer: C) Temporary storage of return addresses and local data
36. The instruction PUSH B means:
A) Store register B contents onto the stack
B) Increment the stack pointer
C) Retrieve B from stack
D) Swap B with accumulator
Answer: A) Store register B contents onto the stack
37. A subroutine can call another subroutine. This process is known as:
A) Linking
B) Nesting
C) Recursion
D) Chaining
Answer: B) Nesting
38. In recursion, each call instance stores its return information in:
A) Accumulator
B) Data segment
C) Stack
D) Control register
Answer: C) Stack
39. The main difference between subroutine and macro is:
A) Subroutine is hardware-level
B) Macro executes faster
C) Macro is expanded at assembly time, subroutine executes at runtime
D) Subroutine has no parameters
Answer: C) Macro is expanded at assembly time, subroutine executes at runtime
40. The “stack pointer” is a register that:
A) Holds the base address of code
B) Points to the top of the stack
C) Stores the next instruction address
D) Indicates overflow conditions
Answer: B) Points to the top of the stack
Program Loops (continued)
41. A loop controlled by a decrementing counter often uses which instruction type?
A) ADD
B) DEC and JNZ (Jump if Not Zero)
C) MOV
D) JMP
Answer: B) DEC and JNZ (Jump if Not Zero)
42. The instruction CMP A, B in assembly usually:
A) Adds A and B
B) Subtracts B from A without storing result
C) Exchanges A and B
D) Clears both operands
Answer: B) Subtracts B from A without storing result
43. A nested loop in assembly language is executed when:
A) Two labels share same name
B) One loop is placed inside another
C) Loop counter overflows
D) The assembler uses pseudo-ops
Answer: B) One loop is placed inside another
44. The instruction JZ LABEL will cause control transfer only when:
A) Carry flag is set
B) Zero flag is set
C) Negative flag is reset
D) Overflow flag is on
Answer: B) Zero flag is set
45. In loop optimization, unrolling refers to:
A) Expanding the loop body to reduce iteration overhead
B) Collapsing multiple loops
C) Using nested labels
D) Removing jump instructions
Answer: A) Expanding the loop body to reduce iteration overhead
46. To terminate a loop after N iterations, the programmer must:
A) Increment PC
B) Use a counter compared against N
C) Call a subroutine
D) Jump to memory address zero
Answer: B) Use a counter compared against N
47. The “branch delay slot” concept applies to:
A) CISC machines
B) Pipelined RISC architectures
C) Microcontrollers
D) Assemblers only
Answer: B) Pipelined RISC architectures
48. In a basic loop, the instruction that causes repetition is:
A) Conditional branch
B) Immediate move
C) Data load
D) Stack push
Answer: A) Conditional branch
49. Infinite loops in machine language typically result from:
A) Always-true branch conditions
B) Stack corruption
C) Hardware interrupt
D) I/O wait
Answer: A) Always-true branch conditions
50. The instruction NOP is used for:
A) No operand process
B) Timing adjustment or pipeline alignment
C) Clearing accumulator
D) Skipping an address
Answer: B) Timing adjustment or pipeline alignment
51. The simplest method of I/O data transfer is:
A) DMA
B) Interrupt-driven
C) Programmed I/O
D) Direct mapping
Answer: C) Programmed I/O
52. In programmed I/O, data transfer occurs:
A) Automatically
B) Under direct CPU control
C) Using DMA controller
D) During power-up only
Answer: B) Under direct CPU control
53. The flag register in I/O programming is used to:
A) Indicate device status
B) Control interrupts
C) Clear buffer
D) Store input data
Answer: A) Indicate device status
54. The instruction IN 01H does what?
A) Sends data to device 01H
B) Reads data from input port 01H into accumulator
C) Reads memory address 01H
D) Resets device 01H
Answer: B) Reads data from input port 01H into accumulator
55. The term “busy waiting” refers to:
A) CPU repeatedly checking device status until ready
B) Device waiting for CPU
C) DMA transfer halt
D) Stack pointer delay
Answer: A) CPU repeatedly checking device status until ready
56. An interrupt allows:
A) Sequential I/O
B) Asynchronous device service without polling
C) Continuous looping
D) Buffer flushing
Answer: B) Asynchronous device service without polling
57. The Interrupt Service Routine (ISR) always ends with:
A) Return from Interrupt (RETI)
B) JMP instruction
C) HALT instruction
D) CALL instruction
Answer: A) Return from Interrupt (RETI)
58. In interrupt-driven I/O, priority among devices is determined by:
A) Hardware or software interrupt priority mechanism
B) Program order
C) Stack pointer
D) Opcode length
Answer: A) Hardware or software interrupt priority mechanism
59. Direct Memory Access (DMA) allows data transfer:
A) Through accumulator
B) Between memory and I/O device without CPU intervention
C) Via stack pointer
D) Using instruction register
Answer: B) Between memory and I/O device without CPU intervention
60. The DMA controller temporarily takes control of:
A) Stack
B) System bus
C) Program counter
D) Control register
Answer: B) System bus
61. The instruction OUT 02H means:
A) Send accumulator content to output port 02H
B) Read from port 02H
C) Load immediate data
D) Clear flag
Answer: A) Send accumulator content to output port 02H
62. In memory-mapped I/O, devices share:
A) Address space with memory
B) Data bus only
C) Interrupt vector table
D) Stack area
Answer: A) Address space with memory
63. Isolated I/O differs from memory-mapped I/O because:
A) Devices use stack area
B) I/O ports have separate address space
C) It is slower
D) It uses ALU flags
Answer: B) I/O ports have separate address space
64. A handshake signal ensures:
A) Continuous interrupts
B) Synchronization between CPU and I/O device
C) Memory protection
D) Clock multiplication
Answer: B) Synchronization between CPU and I/O device
65. The term “port-mapped I/O” refers to:
A) I/O performed via file system
B) Dedicated port addresses for I/O communication
C) Direct access through cache
D) Assembler-level macros
Answer: B) Dedicated port addresses for I/O communication
66. The I/O instruction set is part of:
A) Operating system
B) Processor’s architecture
C) DMA controller
D) Cache unit
Answer: B) Processor’s architecture
67. Input-Output mapping simplifies:
A) Macro expansion
B) Hardware device interfacing
C) Memory fragmentation
D) Cache allocation
Answer: B) Hardware device interfacing
68. During I/O operations, the CPU uses:
A) Status register only
B) Control, data, and status registers
C) ALU buffer
D) Flag register
Answer: B) Control, data, and status registers
69. Interrupt latency is defined as:
A) Execution speed of I/O device
B) Time between interrupt request and ISR execution
C) Number of interrupts handled
D) ISR return delay
Answer: B) Time between interrupt request and ISR execution
70. Vector interrupts mean:
A) Random interrupts
B) Each interrupt has a unique address vector
C) Hardware shared interrupts
D) Non-maskable interrupts
Answer: B) Each interrupt has a unique address vector
71. In assembler design, relocation information is required for:
A) Symbol table generation
B) Adjusting addresses when program is loaded at different locations
C) Instruction scheduling
D) Opcode decoding
Answer: B) Adjusting addresses when program is loaded at different locations
72. Linking loaders primarily handle:
A) Source code translation
B) Combining multiple object modules into a single executable
C) Operand encoding
D) Assembler directives
Answer: B) Combining multiple object modules into a single executable
73. During macro expansion, parameters are:
A) Replaced with actual arguments before code generation
B) Ignored by the assembler
C) Stored in stack
D) Assigned to registers
Answer: A) Replaced with actual arguments before code generation
74. Conditional assembly enables:
A) Assembling certain code segments based on predefined conditions
B) Machine-level branching
C) Label relocation
D) Program halting
Answer: A) Assembling certain code segments based on predefined conditions
75. The assembler’s intermediate file typically contains:
A) Executable binary
B) Symbolic labels only
C) Partially translated code with unresolved addresses
D) Listing of macros only
Answer: C) Partially translated code with unresolved addresses
76. Which statement about assembler passes is true?
A) Both passes perform opcode translation
B) First pass builds symbol table, second pass generates object code
C) Both passes generate machine code
D) Both handle macros
Answer: B) First pass builds symbol table, second pass generates object code
77. A one-pass assembler is suitable when:
A) All labels are defined before use
B) Forward references are allowed
C) Symbol table is not needed
D) Program is very large
Answer: A) All labels are defined before use
78. In relocation, the term “base address” refers to:
A) The start of data segment
B) The address where program is loaded into memory
C) The accumulator address
D) Symbol table location
Answer: B) The address where program is loaded into memory
79. Absolute addressing means:
A) Using base plus offset
B) Directly specifying the memory address of operand
C) Using register reference
D) Using relative offsets
Answer: B) Directly specifying the memory address of operand
80. Indirect addressing allows:
A) Fetching operand address from memory location specified in instruction
B) Direct operand access
C) Register swapping
D) Constant data access
Answer: A) Fetching operand address from memory location specified in instruction
81. The “Return from Subroutine” instruction performs which operation on the stack?
A) Pushes PC value
B) Pops return address into PC
C) Clears top of stack
D) Loads accumulator
Answer: B) Pops return address into PC
82. Reentrant subroutines are designed to:
A) Modify code during execution
B) Allow multiple concurrent executions safely
C) Execute faster
D) Share static data
Answer: B) Allow multiple concurrent executions safely
83. The term “link register” refers to:
A) A register that holds return address during subroutine call
B) Symbol table entry
C) Stack base pointer
D) I/O buffer register
Answer: A) A register that holds return address during subroutine call
84. Parameter passing to subroutines can be achieved via:
A) Memory-mapped I/O
B) Registers, stack, or memory
C) Flag manipulation
D) Interrupt vector
Answer: B) Registers, stack, or memory
85. Recursive subroutines are feasible only when:
A) Stack is not used
B) Each call has its own stack frame
C) Program counter is fixed
D) Symbol table is empty
Answer: B) Each call has its own stack frame
86. Dynamic linking allows:
A) Loading routines at runtime instead of compile time
B) Combining code during assembly
C) Static relocation
D) Symbol elimination
Answer: A) Loading routines at runtime instead of compile time
87. Tail recursion optimization removes:
A) Extra stack frames in recursive calls
B) Loop control logic
C) Symbol references
D) Opcode tables
Answer: A) Extra stack frames in recursive calls
88. A subroutine that modifies global variables without parameter passing leads to:
A) Modular design
B) Side effects
C) Parallel execution
D) Recursion elimination
Answer: B) Side effects
89. In high-level to assembly translation, a “function call” is equivalent to:
A) CALL instruction followed by stack operations
B) A macro expansion
C) A pseudo-op
D) A direct jump
Answer: A) CALL instruction followed by stack operations
90. The RET instruction corresponds to:
A) Pop top of stack into program counter
B) Push return address
C) Jump to base address
D) Skip next instruction
Answer: A) Pop top of stack into program counter
Input/Output and Interrupt Control
91. Non-maskable interrupts (NMI) are:
A) Interrupts that cannot be disabled by software
B) Generated only by user
C) Handled by DMA
D) Lowest priority interrupts
Answer: A) Interrupts that cannot be disabled by software
92. Polling is less efficient because:
A) Device response is unpredictable
B) CPU is busy checking device status repeatedly
C) It needs DMA
D) Stack overflows occur
Answer: B) CPU is busy checking device status repeatedly
93. In vectored interrupt systems, the interrupting device:
A) Supplies the ISR starting address directly
B) Waits for DMA grant
C) Uses polling
D) Uses pseudo-ops
Answer: A) Supplies the ISR starting address directly
94. Priority interrupt controllers manage:
A) Cache lines
B) Multiple interrupt requests based on defined priorities
C) Data bus synchronization
D) Stack overflow
Answer: B) Multiple interrupt requests based on defined priorities
95. The instruction EI does what in many architectures?
A) End interrupt
B) Enable interrupts globally
C) Exchange interrupt vector
D) Execute interrupt routine
Answer: B) Enable interrupts globally
96. During interrupt servicing, context saving ensures:
A) ISR runs faster
B) Original CPU state is restored after ISR completes
C) Stack is cleared
D) Memory is reallocated
Answer: B) Original CPU state is restored after ISR completes
97. Direct I/O control mode requires:
A) DMA controller
B) Operating system scheduling
C) CPU to execute all I/O transfer instructions
D) Parallel bus
Answer: C) CPU to execute all I/O transfer instructions
98. The instruction HLT indicates:
A) Hardware lock
B) Stop execution until reset or interrupt occurs
C) Halt I/O
D) High-level termination
Answer: B) Stop execution until reset or interrupt occurs
99. In asynchronous I/O operations, data transfer occurs:
A) In lock-step with clock
B) Independently of CPU timing signals
C) Only when flags are cleared
D) In one cycle
Answer: B) Independently of CPU timing signals
100. The main purpose of input-output programming in a basic computer is to:
A) Transfer data between registers
B) Control arithmetic operations
C) Interface and synchronize peripheral devices with CPU
D) Manage cache coherency
Answer: C) Interface and synchronize peripheral devices with CPU