Machine Instructions and Addressing Modes in Computer Organization and Architecture MCQ Questions and Answers
1. A machine instruction typically consists of an opcode and operands. Which part tells the CPU what operation to perform?
A. Operand field
B. Addressing mode
C. Opcode
D. Program counter
2. Which addressing mode uses an address specified directly in the instruction?
A. Register indirect
B. Immediate
C. Direct
D. Indexed
3. In the direct addressing mode, the operand is:
A. Taken from a register specified by the instruction
B. Located at the memory address given in the instruction
C. Encoded as part of the instruction bits
D. Found by adding a base register and offset
4. Which addressing mode is best when the constant value must be embedded within the instruction?
A. Direct
B. Register indirect
C. Immediate
D. Base-relative
5. The instruction LOAD R1, 1000 where 1000 is an absolute memory address is an example of:
A. Immediate addressing
B. Direct addressing
C. Register addressing
D. Autoincrement
6. In register addressing, the operand is:
A. Located at a memory address given by the instruction
B. Encoded as a constant within the instruction
C. Stored in a CPU register specified by the instruction
D. Located via an index and base register
7. Which addressing mode allows the effective address to be computed by adding a base register and an offset?
A. Immediate
B. Register
C. Base-plus-offset (base + displacement)
D. Relative
8. The program counter relative addressing mode is most useful for:
A. Global data access
B. Register operations
C. Position-independent code and branching
D. Floating point arithmetic
9. In register indirect addressing, the operand resides:
A. Immediately in the instruction
B. At an address formed by adding two registers
C. In memory at the address contained by a register
D. In a special I/O register
10. Which addressing mode automatically increments a register after accessing memory?
A. Register direct
B. Relative
C. Autoincrement (postincrement)
D. Immediate
11. What does the opcode field size primarily affect in an instruction set?
A. Number of addressing modes
B. Size of registers
C. Number of distinct instructions supported
D. Memory access speed
12. A machine has 16 general-purpose registers; how many bits are needed to encode a register specifier?
A. 2 bits
B. 3 bits
C. 4 bits
D. 8 bits
13. Which instruction format is compact for operations with two register operands and a small opcode?
A. Three-address format
B. Memory-to-memory format
C. Register-register (two-address) format
D. Variable-length format
14. Variable-length instruction encoding is often used to:
A. Simplify CPU microcode
B. Provide a richer set of instruction sizes and modes
C. Force fixed decoding time
D. Reduce register file size
15. In a load-store architecture, memory is accessed by:
A. Any computational instruction
B. Explicit load and store instructions only
C. Implicit memory operands in arithmetic instructions
D. Direct register transfer only
16. The effective address (EA) is:
A. The opcode processed by the CPU
B. The physical address stored in the cache
C. The computed memory address where the operand is located
D. The address of the next instruction
17. Which addressing mode is most compact when repeatedly accessing array elements sequentially?
A. Immediate
B. Register direct
C. Direct
D. Autoincrement (or autodecrement) addressing
18. For a machine with 32-bit instructions and a 6-bit opcode, how many bits remain for operands assuming a single-format fixed length?
A. 16 bits
B. 26 bits
C. 26 bits (32 − 6 = 26)
D. 24 bits
19. In indexed addressing, the effective address is formed by:
A. Adding two immediate values
B. Subtracting base from index
C. Adding an index register to a base or displacement
D. Using only the program counter
20. Which addressing mode supports accessing elements at varying offsets from a base pointer (e.g., structure fields)?
A. Immediate
B. Register direct
C. Base + offset (base-plus-displacement)
D. Relative to stack pointer only
21. The instruction length is often variable to:
A. Guarantee alignment
B. Reduce instruction set complexity
C. Allow short encodings for common instructions and longer ones for complex operations
D. Eliminate the opcode field
22. What does the term operand specifier mean?
A. The opcode that chooses ALU operation
B. The microcode entry number
C. The part of the instruction that indicates where to find or what the operand is
D. The pipeline stage where operand is read
23. When an instruction uses memory indirect addressing, it means:
A. The memory address is directly in the instruction
B. The operand is stored in a register
C. The instruction points to a memory location which contains the actual address of the operand
D. The CPU uses a cache tag for address translation
24. Which addressing mode is most efficient for passing small constants to instructions?
A. Direct
B. Indexed
C. Immediate
D. Register indirect
25. An instruction with two-address format typically:
A. Has separate source and destination registers and a third register for result
B. Overwrites one operand with the result (dest = dest op src)
C. Requires memory access for every operand
D. Is limited to arithmetic operations only
26. In a RISC design, instruction formats are typically:
A. Variable-length and complex
B. Dependent on microcode
C. Fixed-length and simple for fast decoding
D. Eliminated completely
27. Which addressing mode helps implement procedure calls and local variables efficiently?
A. Immediate
B. Direct
C. Stack (stack-relative) addressing
D. Register direct
28. If an instruction set provides 256 opcodes, how many bits are needed for the opcode field?
A. 6 bits
B. 7 bits
C. 8 bits
D. 16 bits
29. In scaled indexed addressing, the index register is multiplied by a scale factor before being added. This is particularly useful for:
A. Immediate constants
B. Accessing array elements of data types larger than 1 byte
C. Fetching instructions from ROM
D. Stack pointer arithmetic
30. Which addressing mode uses the current instruction location as a base for the operand address?
A. Register direct
B. Base-relative addressing
C. Program counter (PC) relative addressing
D. Immediate
31. A machine uses little-endian format. Addressing modes are independent of endianness, but endianness affects:
A. Opcode length
B. Instruction fetch width
C. Byte order within multi-byte data at the computed EA
D. Number of registers
32. In absolute addressing, relocation of programs is harder because:
A. Registers change values at runtime
B. Opcode mapping varies
C. Instruction contains fixed memory addresses that must be updated if program is relocated
D. Cache invalidation occurs
33. Which addressing mode would you use to implement an efficient loop counter decrement and branch?
A. Immediate for all values
B. Register or autodecrement/autoincrement
C. Direct only
D. Indexed only
34. In a hypothetical instruction format: opcode(6) | reg1(5) | reg2(5) | imm(16). What class of instruction format is this?
A. Three-address memory format
B. Register-register with immediate (mixed) format
C. Pure immediate format
D. Floating point only
35. Self-modifying code manipulates instructions in memory. Which addressing mode makes it easiest to locate and modify instructions?
A. Register indirect
B. Immediate
C. Direct (absolute) addressing of instruction memory
D. Indexed with PC
36. Which addressing mode reduces instruction size for frequently used registers?
A. Register addressing (small register specifiers)
B. Immediate addressing
C. Direct addressing
D. Scaled addressing
37. The stack pointer relative addressing mode computes addresses relative to:
A. The base register only
B. The instruction register
C. The top of the stack (stack pointer)
D. The frame pointer always
38. In auto-decrement addressing used for stacks, the sequence for POP is typically:
A. Use then decrement SP
B. Decrement SP then use memory at new SP
C. Increment SP then use memory
D. Use memory then increment SP
39. Which addressing mode is often used for position-independent code and PIC?
A. Absolute
B. Direct
C. PC-relative addressing
D. Immediate
40. When encoding instructions, larger opcode fields allow:
A. Fewer registers
B. More distinct operations/function codes
C. Faster memory access
D. Smaller program size
41. Effective Address = Base Register + Index Register × Scale + Displacement is an expression of which addressing mode?
A. Immediate
B. Register direct
C. Complex addressing (scaled indexed with displacement)
D. Stack addressing
42. In a CISC machine, instruction decoding is typically:
A. Extremely fast and parallel always
B. More complex due to many formats and addressing modes
C. Not necessary because microcode is absent
D. Performed only in hardware without microcode
43. Which addressing mode requires the fewest memory accesses to fetch the operand?
A. Direct
B. Register addressing
C. Register indirect
D. Indexed
44. For a 64-bit architecture, immediate fields are often limited in size. Why?
A. Because registers are smaller
B. Because memory addresses are shorter
C. To keep instruction length reasonable while still supporting 64-bit data via registers
D. Because immediate mode is deprecated
45. Which addressing mode is commonly used for array element access inside loops where the base address is constant?
A. Immediate
B. Direct
C. Indexed (base + index)
D. Register only
46. The indirection level in an addressing mode indicates:
A. The number of bytes in the operand
B. The pipeline stages to fetch operand
C. How many times memory or register must be looked up to arrive at the final operand
D. The ALU operations required
47. Which instruction format is best when instructions frequently reference memory operands directly?
A. Register-register RISC format
B. Memory-to-memory CISC format
C. Pure immediate only
D. Microcoded fixed-length only
48. In two-address instruction format, how many operands can be explicitly named?
A. One
B. Two
C. Two (but one is both source and destination)
D. Three
49. What is the primary advantage of register indirect with displacement over simple register indirect?
A. Smaller instruction size
B. Can access data at an offset from the register (e.g., fields in record)
C. Allows immediate constants
D. Eliminates need for registers
50. Which mode is best suited for accessing function arguments in a stack frame?
A. PC-relative
B. Absolute
C. Frame-pointer or stack-pointer relative addressing
D. Immediate
51. If an instruction has an 8-bit displacement field and uses base addressing, what is the maximum signed offset it can represent?
A. 255
B. 128
C. 127 (signed 8-bit: −128 to +127)
D. 512
52. The addressing mode that computes EA by combining a segment register and an offset is called:
A. Indexed addressing
B. Immediate addressing
C. Segment:offset (segmented) addressing
D. Autoincrement
53. Which addressing mode can cause extra memory access overhead due to pointer chasing?
A. Immediate
B. Register direct
C. Memory indirect (multiple levels of indirection)
D. Indexed
54. In an architecture where opcodes are variable length, a short opcode for common instructions leads to:
A. Worse cache performance
B. Smaller code size for common cases
C. No change in code density
D. Reduced instruction set
55. Which addressing mode is most appropriate for implementing switch-case jump tables?
A. Immediate only
B. Register direct only
C. Indexed addressing using a base table pointer and scaled index
D. Segment addressing
56. A CPU with orthogonal instruction set means:
A. Each instruction has only one addressing mode
B. There are no registers
C. Any instruction can use any addressing mode where appropriate
D. The opcode and addressing mode are fused permanently
57. The instruction ADD R1, (R2)+ denotes:
A. Add immediate to R1
B. Add memory at address in R2 to R1 and then increment R2 (postincrement)
C. Add R2 to R1 without changing R2
D. Add R1 to R2 and then increment R1
58. Which addressing mode is typically encoded by a small field specifying one of several registers?
A. Immediate with long constant
B. Register direct addressing
C. Direct absolute addressing
D. Scaled indexed with big displacement
59. What is the main reason to include addressing modes like autoincrement/autodecrement in instruction sets?
A. To reduce register count
B. To enforce stack discipline strictly
C. To make common memory-access patterns more efficient and compact
D. To avoid caches
60. Effective address calculation adds latency to instruction execution. Which design reduces this latency?
A. Use variable-length opcodes
B. Eliminate registers
C. Use simple fixed addressing modes and hardware address generation unit (AGU)
D. Increase instruction cache size
61. In a load-store machine, arithmetic instructions usually operate on:
A. Memory operands only
B. Registers only
C. Immediate only
D. I/O ports only
62. Which addressing mode is least flexible but fastest for the CPU to decode?
A. Register direct
B. Indexed with scale and displacement
C. Memory indirect with multiple levels
D. PC-relative with long displacement
63. The addressing mode LDA R1, @1000 where @1000 is a pointer stored at memory location 1000 is an example of:
A. Direct addressing
B. Immediate addressing
C. Indirect addressing
D. Indexed addressing
64. When designing instruction encodings, what trade-off exists between opcode space and operand specifier space?
A. No trade-off exists
B. Operand specifiers are always larger
C. More opcode bits reduce bits available for operand specifiers in fixed-length formats
D. Opcode and operand bits are independent
65. Which addressing mode is typically used for table lookups where table base is fixed and entries are uniformly sized?
A. Direct only
B. Immediate
C. Base-plus-index with scale (scaled indexed addressing)
D. Register indirect
66. In systems with virtual memory, the effective address is translated to a physical address by:
A. The ALU directly
B. The instruction decoder
C. MMU (Memory Management Unit) using page tables or TLB
D. The opcode field
67. If a machine uses position-independent code (PIC), which addressing modes are most friendly?
A. Absolute addressing and hard-coded addresses
B. PC-relative and register-based addressing
C. Only immediate addressing
D. Only autoincrement addressing
68. Which addressing mode is likely to produce many cache misses if pointers are poorly localized?
A. Immediate
B. Register direct
C. Register indirect / pointer chasing
D. PC-relative
69. An architecture with many addressing modes increases instruction set complexity but may:
A. Reduce compiler effectiveness
B. Improve code density for some applications
C. Make decoding trivial
D. Prevent use of pipelining
70. The displacement in base-plus-displacement addressing is usually:
A. A register name
B. A small immediate field added to the base register
C. The next instruction opcode
D. The program counter value only
71. Which addressing mode is most suited for accessing global variables at fixed addresses?
A. PC-relative
B. Absolute/direct addressing
C. Stack-relative
D. Autoincrement
72. The instruction MOV R1, [R2 + 4*R3 + 8] uses which addressing concept?
A. Immediate only
B. Register indirect only
C. Scaled indexed with displacement
D. Stack-relative
73. In some ISAs, certain addressing modes are privileged and only allowed in kernel mode. Which would most likely be privileged?
A. Immediate
B. Register direct
C. Direct absolute addressing to I/O memory regions
D. Stack-relative
74. Which addressing mode empowers compilers to implement quick access to structure members?
A. Immediate only
B. PC-relative only
C. Base-plus-offset using a base pointer to the structure
D. Register indirect only
75. The presence of many addressing modes affects pipelining by:
A. Always improving pipeline throughput
B. Removing the need for hazard detection
C. Increasing complexity in the instruction decode and address generation stages
D. Eliminating branch mispredictions
76. Which addressing mode is commonly represented by the syntax [R1] in assembly languages?
A. Immediate
B. Register indirect (memory at address in R1)
C. Indexed with displacement
D. PC-relative
77. A displacement field is most often encoded as:
A. A pointer to a register file
B. A dynamic value computed at runtime only by software
C. A signed/unsigned immediate value included in the instruction
D. The opcode modifier
78. In systems with limited instruction length, compilers prefer:
A. Large immediate fields always
B. Using registers and short addressing modes to fit operands
C. Embedding full memory addresses everywhere
D. Self-modifying code
79. Which addressing mode would typically require two memory accesses to fetch the actual operand (one to fetch pointer, one to fetch data)?
A. Immediate
B. Direct
C. Indirect addressing
D. Register direct
80. In the formula for EA: EA = PC + Displacement, the displacement is usually:
A. A register content
B. A memory location
C. A signed immediate value indicating distance from current PC
D. Always zero
81. Which addressing mode is essential for implementing dynamic data structures like linked lists?
A. Immediate only
B. PC-relative only
C. Pointer-based addressing (register indirect / memory indirect)
D. Absolute only
82. If an instruction set supports autoincrement on operands used for string operations, the typical effect is:
A. The pointer is decremented after use
B. The pointer is incremented automatically so successive elements can be accessed easily
C. The data is zeroed after each access
D. The instruction is converted to immediate form
83. Which addressing mode makes the most sense to use for a return address in function call instructions?
A. Immediate operand with constant 0
B. PC-relative or stack-based storage of return address
C. Register indirect only
D. Absolute fixed memory location
84. Addressing modes that use segment registers are primarily found in:
A. Modern RISC only designs
B. Architectures supporting segmented memory models (e.g., x86 real mode historically)
C. GPUs exclusively
D. Purely stack-based machines
85. What is the purpose of a scale factor in scaled indexed addressing?
A. To select register file bank
B. To indicate endianness
C. To multiply the index register to account for element size (e.g., 4 bytes per element)
D. To specify pipeline priority
86. In CISC architectures, complex addressing modes often reduce code size at the expense of:
A. Larger register files
B. Simpler compilers
C. Increased decode and execution complexity
D. Removing the need for caches
87. Which instruction field typically determines how many operands an instruction has?
A. Displacement field
B. Register file size
C. Opcode or instruction format bits
D. Memory alignment flags
88. In some ISAs, immediate operands are sign-extended when used as signed values. Why is sign-extension necessary?
A. To reduce instruction length
B. To preserve the sign when promoting a smaller immediate to the machine word size
C. To change endianness
D. To encrypt the immediate
89. If an instruction uses memory-to-memory operations, the potential downside is:
A. It simplifies compilation
B. It always uses fewer cycles
C. It often increases memory traffic and reduces register reuse
D. It eliminates addressing modes
90. Which addressing mode encoding allows quick access to frequently used registers with small bit fields?
A. Large absolute addresses in instruction
B. Register direct with compact register specifiers
C. Indirect memory references
D. Scaled indexed with long displacement
91. In a pipelined CPU, address generation for complex modes (scale + index + base) should ideally be:
A. Done in software only
B. Performed by a dedicated address generation unit (AGU) concurrently
C. Deferred until commit stage
D. Ignored by the pipeline
92. Relative addressing is most useful for:
A. Hardware interrupts only
B. Floating point operations
C. Branching and position independent code
D. Cache coherence
93. A displacement field of 12 bits can address how many bytes forward if treated as unsigned?
A. 2048
B. 1024
C. 4096 (2^12 = 4096)
D. 8192
94. Which addressing mode allows both read and write of memory pointed by a register with a single instruction and updates the register?
A. Immediate
B. PC-relative
C. Autoincrement or autodecrement register indirect
D. Indexed without update
95. The concept of orthogonality in ISA design refers to:
A. Instructions only operate on orthogonal matrices
B. The ability to use addressing modes and registers in any combination across instructions
C. Fixed instruction length only
D. Exclusive use of register addressing
96. In many ISAs, certain addressing modes are favored for performance. Which tool (compiler technique) helps take advantage of these modes?
A. Garbage collection
B. Constant folding only
C. Addressing mode selection / instruction selection in the compiler back-end
D. Link-time optimization only
97. Which addressing mode will most likely require relocation entries when creating an executable for a different load address?
A. PC-relative (if displacement is relative)
B. Register direct
C. Absolute/direct addressing containing absolute memory addresses
D. Register indirect with no immediate
98. When an instruction uses a 16-bit signed displacement for PC-relative branching, what is the approximate reachable range in bytes forward/backward?
A. ±32k bytes
B. ±4k bytes
C. ±32,768 bytes (i.e., −32768 to +32767)
D. ±65,536 bytes
99. Which addressing mode is most compact for accessing variables at small fixed offsets from a frame or stack pointer?
A. Absolute addressing
B. PC-relative addressing
C. Stack/frame-pointer relative addressing with small displacement
D. Scaled indexed with full 32-bit displacement
100. A CPU uses a single addressing mode where EA = (base_reg) + (index_reg) × scale + displacement. Which of the following is a major advantage of this unified addressing model?
A. It prevents use of immediate operands
B. It guarantees smaller code size than any other design
C. It is flexible enough to express most common access patterns (arrays, structures, stacks) in a single hardware mechanism
D. It requires no decode hardware