Input-Output Organization MCQ Questions and Answers

1. Which device converts parallel data from the CPU into serial form for transmission over a single line?
A. Printer
B. Parallel port
C. Serial Line Driver
D. DMA controller
Answer: C. Serial Line Driver

2. What is the primary role of an I/O interface?
A. Execute user programs
B. Translate between CPU bus signals and peripheral signals
C. Store long-term data
D. Allocate CPU registers
Answer: B. Translate between CPU bus signals and peripheral signals

3. Which transfer mode requires the CPU to execute explicit instructions for each word transferred?
A. DMA mode
B. Programmed I/O (polling)
C. Interrupt-driven I/O
D. Burst mode
Answer: B. Programmed I/O (polling)

4. In interrupt-driven I/O, the peripheral signals the CPU by asserting what?
A. Memory write
B. Bus grant
C. Interrupt request (IRQ) line
D. DMA enable
Answer: C. Interrupt request (IRQ) line

5. Which of the following is a characteristic of asynchronous data transfer?
A. Requires a shared clock line always
B. Transfers data in fixed-size blocks only
C. Uses start and stop bits for framing
D. Cannot transfer variable-length messages
Answer: C. Uses start and stop bits for framing

6. Which device is primarily responsible for direct memory access without CPU intervention?
A. Serial driver
B. Interrupt controller
C. DMA controller
D. Bus arbiter
Answer: C. DMA controller

7. In priority interrupt handling, a higher priority interrupt can:
A. Be ignored indefinitely
B. Always be processed last
C. Preempt a currently serviced lower-priority interrupt
D. Only be serviced after a full system reset
Answer: C. Preempt a currently serviced lower-priority interrupt

8. What is the advantage of DMA over programmed I/O?
A. More software overhead
B. Lower CPU involvement during data transfer
C. Slower throughput always
D. Requires constant polling
Answer: B. Lower CPU involvement during data transfer

9. Which mode of transfer would typically be used for keyboard input?
A. DMA block transfer
B. Interrupt-driven transfer
C. Programmed I/O in tight loop
D. Memory-mapped burst transfer
Answer: B. Interrupt-driven transfer

10. What does “handshaking” in I/O refer to?
A. Physical handshake between technicians
B. Sending only clocks without data
C. Control signal exchange to synchronize sender and receiver
D. Encrypting I/O data
Answer: C. Control signal exchange to synchronize sender and receiver

11. Which peripheral is most likely memory-mapped rather than port-mapped?
A. Simple status LED
B. CPU internal timer
C. Graphics frame buffer
D. Keyboard controller (on simple ISA)
Answer: C. Graphics frame buffer

12. In a typical UART asynchronous frame, which of these is not present?
A. Start bit
B. Data bits
C. Stop bit
D. Clock bit
Answer: D. Clock bit

13. During DMA transfer, which bus cycle is used by DMA controller to access main memory?
A. Interrupt cycle
B. Bus master cycle (or DMA cycle)
C. Decode cycle
D. Opcode fetch cycle
Answer: B. Bus master cycle (or DMA cycle)

14. Which interrupt type is edge-triggered?
A. Level-triggered only
B. A signal that causes transition detection (e.g., rising edge)
C. Polled only interrupts
D. DMA interrupts exclusively
Answer: B. A signal that causes transition detection (e.g., rising edge)

15. Mode that allows device to transfer a long stream of data with only a single CPU initiation is:
A. Programmed I/O
B. Interrupt per byte
C. DMA block transfer
D. Polled byte transfer
Answer: C. DMA block transfer

16. What is a common purpose of a peripheral controller (device controller)?
A. Compiling code
B. Generating interrupts only
C. Buffering and controlling low-level device operations
D. Increasing CPU clock speed
Answer: C. Buffering and controlling low-level device operations

17. Which of the following is true about memory-mapped I/O?
A. I/O devices occupy separate address space only accessible by IN/OUT instructions
B. I/O devices are assigned addresses within the regular memory address space
C. It cannot use the CPU’s load/store instructions
D. It prohibits DMA usage
Answer: B. I/O devices are assigned addresses within the regular memory address space

18. In a serial communication line, “baud rate” refers to:
A. Bytes per second
B. Signal changes (symbols) per second
C. Bits per block
D. Delay between frames
Answer: B. Signal changes (symbols) per second

19. What is the main disadvantage of polling for I/O?
A. Requires complex hardware only
B. Always slower throughput than DMA
C. Wastes CPU cycles when waiting
D. Cannot handle multiple devices
Answer: C. Wastes CPU cycles when waiting

20. Which signal from the CPU tells a peripheral to put data on the data bus during programmed I/O read?
A. ALE
B. Read (RD) control signal
C. Memory clock
D. Interrupt acknowledge
Answer: B. Read (RD) control signal

21. When an interrupt occurs, the CPU typically does which of the following first?
A. Immediately resume previous process
B. Save the current context
C. Flush main memory
D. Start DMA transfer
Answer: B. Save the current context

22. DMA controller requiring CPU to supply the memory address and count each transfer is called:
A. Independent DMA
B. Fly-by DMA? (incorrect)
C. Cycle stealing DMA
D. Programmed I/O (this is the answer choices; the correct is…)
Answer: C. Cycle stealing DMA
(Note: cycle-stealing DMA interleaves with CPU cycles; one variant has CPU initialize address and count.)

23. What is an interrupt vector?
A. A register storing data bytes
B. The address of the interrupt service routine
C. The DMA channel number
D. A serial communication parameter
Answer: B. The address of the interrupt service routine

24. Which of the following describes “cycle stealing” by DMA?
A. DMA permanently blocks CPU access
B. DMA temporarily takes control of the bus for short transfers, “stealing” cycles
C. CPU steals cycles from DMA
D. Bus arbitration disabling
Answer: B. DMA temporarily takes control of the bus for short transfers, “stealing” cycles

25. The ACHIEVED throughput in serial vs parallel communication for long distance is often:
A. Parallel always faster without exceptions
B. Serial often more reliable and effectively faster at long distances
C. Serial impossible for long distances
D. Parallel and serial identical always
Answer: B. Serial often more reliable and effectively faster at long distances

26. Which mode transfers a byte only when the device is ready and interrupts the CPU on completion?
A. Programmed I/O polling
B. DMA
C. Interrupt-driven I/O
D. Memory-mapped burst
Answer: C. Interrupt-driven I/O

27. Which of the following is true of an interrupt controller like the 8259?
A. It directly reads disk sectors
B. It prioritizes and masks interrupts for the CPU
C. It performs DMA transfers only
D. It executes user programs
Answer: B. It prioritizes and masks interrupts for the CPU

28. In serial communication, parity is used for:
A. Speeding up transfer rate
B. Indicating start of frame
C. Simple error detection
D. Clock recovery only
Answer: C. Simple error detection

29. What is the role of an arbitration mechanism on a shared bus?
A. Encrypt data on the bus
B. Decide which device gets control of the bus at a time
C. Increase voltage levels
D. Convert parallel to serial data
Answer: B. Decide which device gets control of the bus at a time

30. Which of the following is an advantage of interrupt-driven I/O over polling?
A. Higher CPU polling overhead
B. CPU not repeatedly checking device status
C. Guaranteed zero latency
D. No hardware needed
Answer: B. CPU not repeatedly checking device status

31. A device that generates interrupts but does not require immediate service can be classified as:
A. Non-maskable only
B. Maskable interrupt source
C. DMA controller only
D. Polling device only
Answer: B. Maskable interrupt source

32. Which signal assures that the sender and receiver in synchronous transfer share timing?
A. Start bit
B. Stop bit
C. Clock line
D. Parity bit
Answer: C. Clock line

33. Priority encoder in interrupt systems is used to:
A. Encrypt interrupts
B. Generate binary code of highest-priority request
C. Clear DMA channels
D. Schedule disk seeks
Answer: B. Generate binary code of highest-priority request

34. Which statement about polling versus interrupts is correct regarding latency?
A. Polling always has lower latency
B. Interrupts always have higher latency
C. Interrupts usually provide lower average CPU latency to respond when device events are sparse
D. Both have identical latency always
Answer: C. Interrupts usually provide lower average CPU latency to respond when device events are sparse

35. When DMA performs block transfer to memory, the CPU must:
A. Continuously watch each word transferred
B. Just initialize the DMA controller and be interrupted at completion (in many designs)
C. Disable the cache permanently
D. Execute polling until transfer ends
Answer: B. Just initialize the DMA controller and be interrupted at completion (in many designs)

36. Which of the following is NOT typically implemented in device controllers?
A. Data buffering
B. Error detection
C. Formatting of raw signals
D. Compiling user programs
Answer: D. Compiling user programs

37. What is meant by “handshaking lines” like CTS/RTS in serial links?
A. For handshake encryption
B. Signals for flow control between sender and receiver
C. Power lines for the modem
D. Clock signals only
Answer: B. Signals for flow control between sender and receiver

38. Which of the following best describes “spurious interrupt”?
A. A valid high-priority interrupt
B. An interrupt that has no device source or was transient/false
C. A DMA error state
D. A blocked interrupt vector
Answer: B. An interrupt that has no device source or was transient/false

39. In a typical I/O mapped (port-mapped) scheme, which CPU instruction set is used to access ports?
A. Only store/load working registers
B. IN/OUT (in x86 family) or special port instructions
C. DMA transfer calls
D. All normal memory loads/stores with no difference
Answer: B. IN/OUT (in x86 family) or special port instructions

40. Which interface standard is commonly used for high-speed serial peripheral interconnection on motherboards?
A. UART only
B. PCI Express (serial, point-to-point)
C. Parallel ATA only
D. Centronics parallel port
Answer: B. PCI Express (serial, point-to-point)

41. Which technique reduces CPU involvement and allows overlap of computation and I/O?
A. Busy-wait polling
B. DMA-based transfers
C. Synchronous polling only
D. Single-threaded execution
Answer: B. DMA-based transfers

42. Which of the following is an example of a non-maskable interrupt (NMI)?
A. Keyboard typed character
B. Low-priority timer tick
C. Power-fail or hardware fault signal
D. Printer status ready
Answer: C. Power-fail or hardware fault signal

43. In serial transmission, which encoding embeds clocking information with data?
A. ASCII only
B. Manchester encoding
C. Parity-only encoding
D. DMA encoding
Answer: B. Manchester encoding

44. Which DMA mode gives full control of the bus to DMA until the block is transferred?
A. Cycle stealing mode
B. Burst mode (block mode)
C. Interrupt mode
D. Polled mode
Answer: B. Burst mode (block mode)

45. What does “latency” refer to in the context of interrupts?
A. The speed of the bus only
B. Time from device interrupt to start of ISR execution
C. Number of bits per word
D. DMA throughput measured in MB/s
Answer: B. Time from device interrupt to start of ISR execution

46. Which condition typically requires flow control in serial communications?
A. Device and CPU have same speed always
B. Receiver is slower than sender leading to buffer overflow risk
C. DMA controller is idle
D. Parallel transfer is used
Answer: B. Receiver is slower than sender leading to buffer overflow risk

47. For polled I/O, which CPU instruction sequence is most common?
A. Start DMA then sleep
B. Load status register → test bit → branch if not ready → perform I/O
C. Ignore device interrupts
D. Send interrupt to device
Answer: B. Load status register → test bit → branch if not ready → perform I/O

48. An advantage of memory-mapped I/O is:
A. Requires special I/O instructions only
B. Uniform addressing; device registers can be accessed by normal load/store instructions
C. Prevents using caches always
D. Eliminates the need for device drivers
Answer: B. Uniform addressing; device registers can be accessed by normal load/store instructions

49. Which field in a UART frame indicates the end of a byte?
A. Start bit
B. Parity bit
C. Stop bit
D. Address bit
Answer: C. Stop bit

50. Which of the following is true about interrupt nesting?
A. New interrupts are always ignored
B. A higher-priority interrupt can interrupt the currently executing ISR
C. Lower-priority interrupts always preempt higher-priority ones
D. Nesting is impossible in modern systems
Answer: B. A higher-priority interrupt can interrupt the currently executing ISR

51. The main reason to use DMA for disk transfers is:
A. Disables interrupts permanently
B. To transfer large blocks efficiently without occupying CPU
C. To encrypt disk data on the fly
D. To avoid using disk controllers
Answer: B. To transfer large blocks efficiently without occupying CPU

52. Which of the following is an input device example that benefits from interrupt-driven I/O?
A. Hard disk bulk read
B. Keyboard
C. High-speed network card bulk transfer only
D. Simple LED
Answer: B. Keyboard

53. In prioritized interrupt scheme with fixed priorities, starvation of low-priority interrupts can occur because:
A. Low-priority interrupts are faster
B. High-priority interrupts continually preempt lower ones
C. DMA always blocks all interrupts
D. Priority scheme is fair by definition
Answer: B. High-priority interrupts continually preempt lower ones

54. What is the function of RTS (Request To Send) in serial communications?
A. Clock signal for data bits
B. An output control line indicating sender wants to transmit
C. Parity generation
D. DMA activation
Answer: B. An output control line indicating sender wants to transmit

55. Which statement about asynchronous vs synchronous transfer is correct?
A. Asynchronous always faster than synchronous
B. Synchronous transfers use a shared clock, asynchronous uses start/stop bits
C. Asynchronous requires clocks on both ends always
D. Synchronous cannot transfer variable length data
Answer: B. Synchronous transfers use a shared clock, asynchronous uses start/stop bits

56. What is the role of an “interrupt acknowledge” cycle?
A. To start DMA transfer
B. CPU signals to the interrupt controller that it is ready to accept interrupt vector
C. To stop the clock line in serial link
D. To flush caches only
Answer: B. CPU signals to the interrupt controller that it is ready to accept interrupt vector

57. Which bus signal would a device assert to request a DMA transfer?
A. Clock only
B. Bus request (BR) or DMA request line
C. Interrupt acknowledge
D. Parity line
Answer: B. Bus request (BR) or DMA request line

58. Which is a typical feature of high-speed serial links like USB or PCIe?
A. They use wide parallel cables externally
B. Packet-based transfers and embedded clock recovery
C. Always require explicit start/stop bits per byte
D. No error detection or flow control
Answer: B. Packet-based transfers and embedded clock recovery

59. Which I/O method requires the fewest CPU instructions per word transferred?
A. Programmed I/O polling
B. Interrupt per byte
C. DMA block mode
D. Manual bit-banging
Answer: C. DMA block mode

60. In vectored interrupts, the vector contains:
A. The device’s serial number
B. Address or index of the ISR for that interrupt
C. Memory data to be transferred by DMA
D. The CPU clock value
Answer: B. Address or index of the ISR for that interrupt

61. Which device would commonly use programmed I/O due to low transfer rates?
A. High-speed NIC
B. Simple GPIO or status LED
C. Disk controller for large file transfers
D. Video frame buffer
Answer: B. Simple GPIO or status LED

62. Which of the following is true for “latency” vs “throughput” tradeoff in DMA?
A. DMA has infinite latency always
B. DMA may increase throughput but can introduce latency for CPU access to memory during transfers
C. DMA always reduces throughput
D. Latency and throughput are identical concepts
Answer: B. DMA may increase throughput but can introduce latency for CPU access to memory during transfers

63. What is the meaning of “full-duplex” serial communication?
A. Data flows in one direction only
B. Simultaneous two-way data transmission
C. Half the bits used for parity
D. Uses two separate clocks only
Answer: B. Simultaneous two-way data transmission

64. Which of the following best describes memory-mapped device registers?
A. Accessed only by IN/OUT instructions
B. Mapped into the system address space and accessed like memory
C. Always cached by CPU caches without exceptions
D. Only for DMA controllers strictly
Answer: B. Mapped into the system address space and accessed like memory

65. What is the principal drawback of using very high interrupt rates?
A. Interrupts increase DMA speed
B. High context-switch overhead and CPU time spent in ISRs
C. No effect on system performance
D. Reduces device latency to zero always
Answer: B. High context-switch overhead and CPU time spent in ISRs

66. Which of the following is an advantage of serial communication over parallel for long distances?
A. More wires means less crosstalk
B. Lower cost/wiring complexity and less signal skew
C. Always lower latency
D. No need for clock recovery
Answer: B. Lower cost/wiring complexity and less signal skew

67. In asynchronous serial communication, if parity bit is used and does not match expected parity, what happens?
A. Data always accepted silently
B. Receiver detects a parity error and may request retransmission or flag error
C. Clock gets reset at sender
D. DMA starts automatically
Answer: B. Receiver detects a parity error and may request retransmission or flag error

68. What does “bus master” refer to in DMA context?
A. A peripheral that only listens
B. An entity that can take control of the bus and initiate transfers (e.g., DMA controller)
C. CPU cache controller only
D. A priority encoder only
Answer: B. An entity that can take control of the bus and initiate transfers (e.g., DMA controller)

69. Which is true about Non-Maskable Interrupt (NMI) compared to maskable interrupts?
A. NMI can be turned off by software always
B. NMI cannot be disabled by standard masking and indicates critical conditions
C. NMI is lower priority than all other interrupts
D. NMIs are used for regular keyboard input
Answer: B. NMI cannot be disabled by standard masking and indicates critical conditions

70. In an I/O interface, what is the role of a status register?
A. Store user data persistently
B. Execute instructions
C. Hold device state bits like ready, busy, error
D. Increase CPU clock speed
Answer: C. Hold device state bits like ready, busy, error

71. A peripheral using interrupt coalescing will:
A. Immediately interrupt on every event only
B. Group multiple events before raising a single interrupt to reduce interrupt rate
C. Disable DMA permanently
D. Use polling always
Answer: B. Group multiple events before raising a single interrupt to reduce interrupt rate

72. What happens during an interrupt acknowledge cycle on the x86 architecture?
A. The CPU enables DMA channels only
B. CPU reads an interrupt vector provided by the PIC or APIC
C. The CPU sends RD/WR signals to a disk only
D. System clock gets resynchronized
Answer: B. CPU reads an interrupt vector provided by the PIC or APIC

73. What does “bit stuffing” accomplish in synchronous serial protocols like HDLC?
A. Encrypts the data
B. Prevents accidental flag pattern occurrences by inserting extra bits
C. Speeds up clock recovery
D. Adds parity for error detection only
Answer: B. Prevents accidental flag pattern occurrences by inserting extra bits

74. Which of these is true for DMA scatter-gather?
A. Single contiguous block only supported
B. Allows DMA controller to transfer to/from multiple memory segments without CPU moving data
C. Requires CPU to program every word individually
D. Is only for serial ports exclusively
Answer: B. Allows DMA controller to transfer to/from multiple memory segments without CPU moving data

75. What does “interrupt masking” accomplish?
A. Encrypts interrupts on the wire
B. Temporarily disables selected interrupts from being delivered
C. Converts interrupts into DMA cycles
D. Forces immediate interrupt service always
Answer: B. Temporarily disables selected interrupts from being delivered

76. Which mode is simplest for implementing I/O in embedded microcontrollers for slow devices?
A. DMA only
B. Polling (programmed I/O)
C. Burst mode only
D. Interrupt nesting exclusively
Answer: B. Polling (programmed I/O)

77. Which is a real benefit of using serial links with embedded clocking?
A. Requires extra clock wire always
B. Receivers can recover timing from data stream, reducing wiring
C. Cannot achieve high speeds
D. Parity bits are unnecessary always
Answer: B. Receivers can recover timing from data stream, reducing wiring

78. When an I/O device asserts DRQ (DMA request), the next step usually is:
A. CPU immediately halts forever
B. DMA controller requests bus and CPU grants bus (bus grant)
C. Device performs CPU context switch
D. Interrupt vector is sent directly to device
Answer: B. DMA controller requests bus and CPU grants bus (bus grant)

79. Which of the following is NOT an example of serial synchronous protocol?
A. SPI
B. I²C
C. RS-232 (basic RS-232 is asynchronous)
D. PCIe (uses embedded clocking)
Answer: C. RS-232 (basic RS-232 is asynchronous)

80. Which hardware component reduces interrupt handling overhead by aggregating multiple event notifications?
A. Simple LED
B. Network card with interrupt moderation/coalescing
C. UART with no FIFO
D. Polling loop only
Answer: B. Network card with interrupt moderation/coalescing

81. Which one is essential for hot-plugging peripheral devices on a bus?
A. Always programmed I/O only
B. Bus arbitration and event (connect/disconnect) detection mechanisms
C. DMA exclusively
D. Interrupt masking removal only
Answer: B. Bus arbitration and event (connect/disconnect) detection mechanisms

82. In a typical DMA transfer, which register is NOT directly used by the DMA controller?
A. Memory address register
B. Byte count register
C. I/O device data register
D. CPU instruction pointer (IP)
Answer: D. CPU instruction pointer (IP)

83. What is the main goal of flow control in serial links like XON/XOFF?
A. Encrypt the data stream
B. Allow receiver to tell sender to pause/resume when buffers are full
C. Increase baud rate automatically
D. Start DMA transfers without CPU
Answer: B. Allow receiver to tell sender to pause/resume when buffers are full

84. For vectored interrupts, which entity often supplies the vector to the CPU?
A. The DMA controller only
B. The interrupt controller (PIC/APIC) or device
C. The CPU itself always
D. The memory controller exclusively
Answer: B. The interrupt controller (PIC/APIC) or device

85. Edge-triggered interrupts differ from level-triggered interrupts because:
A. Edge triggers when level stable only
B. Edge detects transitions; level detects sustained signal level
C. Edge interrupts never get serviced
D. Level interrupts are always higher priority
Answer: B. Edge detects transitions; level detects sustained signal level

86. Which I/O transfer mode is most suitable for streaming audio with low CPU usage?
A. Polled byte-by-byte I/O
B. DMA with double buffering
C. Single interrupt per sample
D. Busy-wait loop only
Answer: B. DMA with double buffering

87. In serial asynchronous communication, if both ends agree on 8N1 framing, that means:
A. 8 start bits, no parity, 1 stop bit
B. 8 data bits, No parity, 1 stop bit
C. 8 parity bits only
D. No start/stop bits required
Answer: B. 8 data bits, No parity, 1 stop bit

88. What is the function of a FIFO in a UART device?
A. Only convert parallel to serial
B. Buffer multiple received/transmitted bytes to reduce interrupt rate
C. Provide DMA without CPU setup
D. Store long-term files
Answer: B. Buffer multiple received/transmitted bytes to reduce interrupt rate

89. In DMA-based disk transfer, which event typically notifies the CPU that transfer is complete?
A. DMA never notifies CPU
B. DMA completion interrupt
C. CPU polls disk continuously
D. Transfer finishes silently with no status change
Answer: B. DMA completion interrupt

90. Which method allows multiple devices to share a single interrupt line and still be identified?
A. Dedicated IRQs only
B. Polling of all devices after shared interrupt to identify source
C. DMA only
D. Serializing interrupts automatically without polling
Answer: B. Polling of all devices after shared interrupt to identify source

91. Which of these is used to control access to a shared bus among multiple masters?
A. Parity generator
B. Bus arbiter
C. UART FIFO
D. Interrupt vector table
Answer: B. Bus arbiter

92. What is the effect of disabling interrupts during critical section in OS?
A. Increases chance of interrupt storms
B. Prevents ISRs from preempting the critical section (but may increase interrupt latency)
C. Automatically invokes DMA to finish tasks
D. Flushes device FIFOs always
Answer: B. Prevents ISRs from preempting the critical section (but may increase interrupt latency)

93. Which of the following is an example of character-oriented synchronous protocol?
A. Pure asynchronous with start/stop bits only
B. PPP with HDLC-like framing (byte/character-oriented link-layer framing)
C. Raw DMA transfers without framing
D. IN/OUT memory mapping only
Answer: B. PPP with HDLC-like framing (byte/character-oriented link-layer framing)

94. Which of the following best describes “bus contention”?
A. Normal state when only one device uses bus
B. Simultaneous attempts by multiple devices to drive/control the bus causing conflict
C. A DMA mode name
D. Exclusive to serial communication only
Answer: B. Simultaneous attempts by multiple devices to drive/control the bus causing conflict

95. If a peripheral uses interrupt-driven I/O with no buffering and the CPU is delayed, what can happen?
A. DMA is automatically invoked always
B. Data loss due to device overwriting unserviced data
C. Device will disable itself forever
D. CPU will gain extra cycles automatically
Answer: B. Data loss due to device overwriting unserviced data

96. Which is true regarding memory caching and memory-mapped I/O?
A. Caches always beneficial for device registers
B. Device registers usually must be uncached or use cache-coherent mechanisms to avoid stale data
C. Cache coherence never matters for I/O
D. DMA automatically updates CPU registers bypassing memory
Answer: B. Device registers usually must be uncached or use cache-coherent mechanisms to avoid stale data

97. In SPI (Serial Peripheral Interface), which device typically provides the clock?
A. Slave only
B. Master
C. Any slave arbitrarily
D. DMA controller
Answer: B. Master

98. What is the typical reason for using double buffering in DMA transfers?
A. To slow down transfers intentionally
B. To overlap processing and data transfer and avoid gaps or buffer underruns
C. To avoid using interrupts at all costs
D. To force polling instead of interrupts
Answer: B. To overlap processing and data transfer and avoid gaps or buffer underruns

99. Which mechanism allows hot-swappable USB devices to be notified and initialized without reboot?
A. Legacy IN/OUT port only
B. Plug-and-play with interrupt/event notifications and driver loading
C. DMA only
D. Polling every microsecond by CPU
Answer: B. Plug-and-play with interrupt/event notifications and driver loading

100. Which statement about serial communication error detection is correct?
A. Parity detects all multi-bit errors always
B. Checksums are never used in serial links
C. Parity and CRC provide different levels of error detection; CRC is stronger than simple parity
D. Error detection is unnecessary on noisy links
Answer: C. Parity and CRC provide different levels of error detection; CRC is stronger than simple parity