Central Processing Unit MCQ Questions and Answers

1. Which of the following best describes a general register organization?
A. All operations are performed only on memory locations
B. A fixed set of registers specially assigned for I/O only
C. A set of general-purpose registers usable by instructions for operands and results
D. Only one accumulator register is used for all arithmetic
Answer: C. A set of general-purpose registers usable by instructions for operands and results

2. In a register-register (register-to-register) instruction, operands are fetched from:
A. Main memory only
B. General-purpose registers
C. Stack top only
D. Cache lines exclusively
Answer: B. General-purpose registers

3. Which advantage is typically associated with having many general-purpose registers?
A. Increased memory latency
B. Reduced instruction length always
C. Fewer memory accesses and improved performance
D. Increased software complexity for addressing modes only
Answer: C. Fewer memory accesses and improved performance

4. In general register organization, which register type holds the address of the next instruction?
A. Stack Pointer (SP)
B. Program Counter (PC)
C. Memory Address Register (MAR)
D. Instruction Register (IR)
Answer: B. Program Counter (PC)

5. Which register is commonly used to hold intermediate results in a general register machine?
A. Status Register only
B. Any general-purpose register
C. Only the accumulator
D. Only special floating-point registers
Answer: B. Any general-purpose register

6. In a load/store architecture, arithmetic instructions:
A. Operate directly on memory operands
B. Require operands to be in registers before arithmetic
C. Always use immediate values only
D. Never use registers
Answer: B. Require operands to be in registers before arithmetic

7. Which of the following is a characteristic of a load-store (RISC-style) design?
A. Complex addressing in arithmetic instructions
B. Many specialized instruction formats with varying lengths
C. Separate load and store instructions for memory access
D. Memory-to-memory arithmetic by default
Answer: C. Separate load and store instructions for memory access

8. What is the purpose of register windows (in some RISC designs)?
A. To provide virtual memory mapping for registers
B. To furnish overlapping sets of registers to speed up procedure calls
C. To increase cache associativity
D. To reduce the number of instruction formats
Answer: B. To furnish overlapping sets of registers to speed up procedure calls

9. In the context of register organization, register aliasing refers to:
A. Two different registers mapping to the same physical register
B. Register contents being stored only in cache
C. Renaming registers in assembly listings only
D. Having registers only for floating-point use
Answer: A. Two different registers mapping to the same physical register

10. Which hazard is directly reduced by having a large register file and register renaming?
A. Structural hazards only
B. Control hazards only
C. Data hazards due to false dependencies (WAR/WAW)
D. Page faults
Answer: C. Data hazards due to false dependencies (WAR/WAW)

11. In stack organization, where is the top-of-stack typically found?
A. A dedicated stack pointer register (SP)
B. Program Counter (PC)
C. Memory Address Register (MAR)
D. Instruction Register (IR)
Answer: A. A dedicated stack pointer register (SP)

12. The primary operation used for adding an element to a stack is called:
A. POP
B. FETCH
C. PUSH
D. ALLOCATE
Answer: C. PUSH

13. Which instruction removes the top element from the stack?
A. PUSH
B. POP
C. TOP
D. READ
Answer: B. POP

14. Which organization naturally supports reverse Polish notation (RPN) style expression evaluation?
A. Accumulator organization
B. Stack organization
C. Register-memory organization
D. Memory-to-memory organization
Answer: B. Stack organization

15. One main advantage of stack machines is:
A. Reduced need for registers in code generation
B. Faster random access to arbitrary memory
C. Larger instruction set complexity
D. Unlimited stack size hardware support
Answer: A. Reduced need for registers in code generation

16. Which is a disadvantage of stack-based CPU organization?
A. Simple compiler design
B. Inefficient access to deep stack elements compared to registers
C. Fewer memory accesses
D. Easily parallelizable instruction execution
Answer: B. Inefficient access to deep stack elements compared to registers

17. For function calls, stack organization commonly uses which of the following to store return addresses and local variables?
A. Global registers only
B. Heap memory only
C. Activation records on the call stack
D. Instruction cache entries
Answer: C. Activation records on the call stack

18. In a stack machine, which of the following instructions would typically both pop two operands and push one result?
A. LOAD
B. CALL
C. ADD (binary arithmetic)
D. JUMP
Answer: C. ADD (binary arithmetic)

19. A postfix expression evaluation on a stack involves which sequence for expression 3 4 + 5 *?
A. Compute (3 + 4) then multiply by 5 using stack operations
B. Convert to infix then evaluate directly in memory
C. Use registers exclusively for evaluation
D. Evaluate as 3 × (4 + 5)
Answer: A. Compute (3 + 4) then multiply by 5 using stack operations

20. A return-from-call instruction in stack-based architectures typically:
A. Pops the return address and jumps to it
B. Reads the return address from the instruction register
C. Writes the return address to main memory then halts
D. Increments the stack pointer only without jumping
Answer: A. Pops the return address and jumps to it

21. In instruction formats, what does the opcode field specify?
A. The memory address to load from
B. The specific operation that the CPU must perform
C. The register mapping to virtual memory
D. The next instruction’s contents
Answer: B. The specific operation that the CPU must perform

22. Which instruction format style uses separate fields for source register, destination register, and opcode often with fixed length?
A. Variable-length stack instruction format
B. Register-register (R-type) fixed format (typical RISC)
C. Notation-based format only used in microcontrollers
D. Memory-memory format with no registers
Answer: B. Register-register (R-type) fixed format (typical RISC)

23. Which format is common in CISC ISAs where instructions can have varying lengths and operand specifiers?
A. Fixed-length three-register R-type only
B. Variable-length instruction formats with many addressing fields
C. Only single-byte opcodes with no operands
D. Stack-only one-byte instructions exclusively
Answer: B. Variable-length instruction formats with many addressing fields

24. In a typical RISC instruction format, which field is intentionally minimized to keep instructions simple?
A. Opcode field
B. Immediate field always set to maximum size
C. Complex addressing mode descriptors
D. Condition code field for every instruction
Answer: C. Complex addressing mode descriptors

25. An instruction with opcode and a large immediate constant often uses which format?
A. R-type register-register format only
B. I-type (immediate) instruction format
C. Stack-only format
D. Floating-point-only format
Answer: B. I-type (immediate) instruction format

26. Which instruction format makes it easy to pipeline?
A. Variable-length, complex decode formats
B. Fixed-length R-type (uniform) formats
C. Formats dependent on memory page size only
D. Formats that embed microcode sequences in each instruction
Answer: B. Fixed-length R-type (uniform) formats

27. The format field that describes addressing mode in an instruction is most useful for:
A. Speeding up floating-point multiply only
B. Determining how to compute the effective address of operands
C. Increasing register file size automatically
D. Inlining function calls during execution
Answer: B. Determining how to compute the effective address of operands

28. Which of the following is NOT an instruction format component?
A. Opcode
B. Operand specifiers
C. Compiler optimization flag stored in the instruction word
D. Immediate value
Answer: C. Compiler optimization flag stored in the instruction word

29. A two-operand instruction format typically:
A. Uses separate registers for source and destination but overwrites destination with result
B. Always preserves both operands in memory
C. Is identical to three-operand format in all ways
D. Is only used for branch instructions
Answer: A. Uses separate registers for source and destination but overwrites destination with result

30. Which of the following describes microcoded variable-width instruction formats?
A. All instructions are executed in a single clock cycle always
B. Some instructions require multiple micro-operations and possibly variable bytes in encoding
C. They are only used in RISC processors
D. They forbid addressing modes
Answer: B. Some instructions require multiple micro-operations and possibly variable bytes in encoding

31. Which addressing mode uses the value contained directly in the instruction as the operand?
A. Register indirect addressing
B. Immediate addressing
C. Index addressing
D. Base-plus-offset addressing
Answer: B. Immediate addressing

32. In register direct addressing, the operand is:
A. Found at the memory address specified in the instruction
B. Contained in a register whose number is specified in the instruction
C. Always an immediate constant
D. Placed on the stack only
Answer: B. Contained in a register whose number is specified in the instruction

33. In register indirect addressing, the instruction specifies a register that:
A. Contains the operand directly
B. Holds the memory address where the operand is located
C. Contains the immediate value to be used
D. Is used only for indexing into code segments
Answer: B. Holds the memory address where the operand is located

34. Which addressing mode adds an index register value to a base address to form an effective address?
A. Immediate addressing
B. Indexed (or base+index) addressing
C. Register direct addressing
D. Relative addressing only for branches
Answer: B. Indexed (or base+index) addressing

35. Relative addressing for PC-relative jumps uses:
A. Absolute memory addresses hard-coded in the instruction only
B. A displacement added to the program counter to compute target address
C. The stack pointer instead of program counter
D. Index registers only, never PC
Answer: B. A displacement added to the program counter to compute target address

36. Which mode is most convenient for accessing array elements?
A. Immediate addressing only
B. Indexed addressing (base + index)
C. Register direct with no base
D. Relative addressing for branches
Answer: B. Indexed addressing (base + index)

37. What is auto-increment addressing?
A. A form of addressing that increments memory after a page fault
B. A mode where the register used as pointer is incremented automatically after access
C. A compiler-level optimization, not an addressing mode
D. Register renaming scheme for pipelining
Answer: B. A mode where the register used as pointer is incremented automatically after access

38. Which addressing mode can be used to implement parameter passing for procedures efficiently?
A. Immediate addressing only
B. Stack addressing (using push/pop and SP)
C. Self-modifying code addressing only
D. Cache-based addressing exclusively
Answer: B. Stack addressing (using push/pop and SP)

39. Which addressing mode consumes fewer instruction bytes when small displacements are used?
A. Register direct always
B. PC-relative addressing with small displacement
C. Complex multi-level indirect addressing always
D. Indexed addressing with large indices only
Answer: B. PC-relative addressing with small displacement

40. Which addressing mode is most likely to require extra memory accesses to follow pointers?
A. Immediate addressing
B. Direct (absolute) addressing with no indirection
C. Indirect addressing (pointer to pointer)
D. Register direct addressing
Answer: C. Indirect addressing (pointer to pointer)

41. RISC architectures tend to emphasize which of the following?
A. Complex CISC-like microcoded instructions
B. Large number of addressing modes in each instruction
C. Simplicity: fixed instruction length, load/store model, few addressing modes
D. Emulation of variable-length instruction sets at hardware level only
Answer: C. Simplicity: fixed instruction length, load/store model, few addressing modes

42. Which attribute is commonly associated with RISC instruction sets?
A. Many specialized memory-to-memory arithmetic instructions
B. One instruction per clock cycle in simplified pipelines (often)
C. Widely varying instruction lengths for complex addressing
D. Mandatory microcode for every instruction
Answer: B. One instruction per clock cycle in simplified pipelines (often)

43. A defining characteristic of RISC pipelines is:
A. Complex decode stage taking many cycles
B. Uniform instruction format that eases pipelining and parallelism
C. Always microcoded control sequences for micro-ops
D. Execution of multiple addressing modes inside each ALU operation
Answer: B. Uniform instruction format that eases pipelining and parallelism

44. Which instruction set philosophy emphasizes many addressing modes and complex single instructions?
A. RISC
B. CISC
C. VLIW only
D. SIMD exclusively
Answer: B. CISC

45. In RISC vs CISC debate, CISC’s complex instructions usually aim to:
A. Reduce the number of instructions per program by handling high-level operations in hardware
B. Make pipelining trivial and always single-cycle
C. Eliminate the need for a compiler
D. Increase register file size only
Answer: A. Reduce the number of instructions per program by handling high-level operations in hardware

46. Which architecture typically uses microcode to implement complex instructions?
A. RISC, always
B. CISC, often
C. Neither RISC nor CISC uses microcode ever
D. Only GPUs use microcode, CPUs never do
Answer: B. CISC, often

47. Which design typically results in compact code density (smaller total program size)?
A. RISC, always
B. CISC, often due to complex multi-step instructions
C. Neither — both produce equal code density always
D. Only stack machines produce compact code density
Answer: B. CISC, often due to complex multi-step instructions

48. RISC designs favor simplicity to improve:
A. Microcode store size only
B. Compiler performance, pipelining, and clock frequency
C. Complexity of instruction decoding exclusively
D. Memory fragmentation only
Answer: B. Compiler performance, pipelining, and clock frequency

49. Which of the following best explains why modern processors blend RISC and CISC ideas?
A. RISC and CISC are mutually exclusive and cannot be combined
B. Designers take simple pipelined cores (RISC) and add microcode or complex decode for compatibility (CISC)
C. To increase instruction length to 512 bits always
D. To abandon pipelining entirely
Answer: B. Designers take simple pipelined cores (RISC) and add microcode or complex decode for compatibility (CISC)

50. Which term refers to the RISC idea of keeping most instructions at a single fixed length?
A. Variable-width ISA
B. Uniform instruction encoding
C. Microcoded instruction set only
D. Stack-oriented encoding only
Answer: B. Uniform instruction encoding

51. An instruction format that allows three register operands (two sources and one destination) is often favored because:
A. It increases the need to access memory for every operation
B. It avoids overwriting source operands and simplifies compiler code generation
C. It prohibits compiler optimization
D. It is only used for microcoded instructions
Answer: B. It avoids overwriting source operands and simplifies compiler code generation

52. Which addressing mode would typically use the content of a base register plus a signed offset stored in the instruction?
A. Immediate addressing
B. Base + offset addressing (also called displacement addressing)
C. Stack addressing only
D. Register indirect without offset
Answer: B. Base + offset addressing (also called displacement addressing)

53. In CISC architectures, complex addressing modes can lead to which hardware consequence?
A. Simpler decode logic
B. Longer and more complex instruction decode and address calculation stages
C. No effect on pipeline stages
D. Guaranteed single-cycle memory access
Answer: B. Longer and more complex instruction decode and address calculation stages

54. Which addressing mode allows self-modifying pointers like increment-on-access without separate increment instructions?
A. Register direct addressing
B. Auto-increment or auto-decrement addressing modes
C. Immediate addressing only
D. Relative addressing for branches
Answer: B. Auto-increment or auto-decrement addressing modes

55. Which is the main reason CISC historically included many addressing modes?
A. To make compiler writing trivial and reduce code size by handling many tasks in single instructions
B. To ensure every instruction uses registers only
C. To remove the need for memory altogether
D. To maximize pipeline throughput always
Answer: A. To make compiler writing trivial and reduce code size by handling many tasks in single instructions

56. In instruction formats, which field often controls conditional execution in some ISAs?
A. Addressing mode field only
B. Condition or predicate field
C. Opcode field never contains condition info
D. Stack pointer field only
Answer: B. Condition or predicate field

57. Which addressing mode is most suitable for jump tables in switch-case constructs?
A. Indexed or indirect through table base and index register
B. Immediate addressing only
C. Register direct for floating point only
D. Auto-decrement only
Answer: A. Indexed or indirect through table base and index register

58. Which instruction type is likely to be micro-coded in a CISC machine?
A. Simple register-to-register ADD always
B. Complex string or block move operations that perform multiple memory transfers
C. Single-cycle NOP
D. Standard load/store only
Answer: B. Complex string or block move operations that perform multiple memory transfers

59. In a stacked-based instruction set, which instruction sequence best represents the evaluation of A + B where A and B are memory variables?
A. LOAD R1, A; LOAD R2, B; ADD R1, R2
B. PUSH A; PUSH B; ADD; POP result
C. MOVE A, B; ADD B, A
D. JUMP to A; JUMP to B; ADD
Answer: B. PUSH A; PUSH B; ADD; POP result

60. Which addressing mode is used when an instruction contains the memory address of the operand explicitly?
A. Immediate addressing
B. Direct (absolute) addressing
C. Register indirect addressing
D. Indexed addressing only
Answer: B. Direct (absolute) addressing

61. The complexity of address calculation in an instruction primarily affects:
A. Only compiler optimization, not hardware
B. Instruction fetch and decode latency and pipeline complexity
C. Only I/O throughput
D. The color of LEDs on the motherboard
Answer: B. Instruction fetch and decode latency and pipeline complexity

62. Which of the following best describes a typical RISC compiler’s role given the ISA design?
A. Relying heavily on compiler to combine simple instructions into complex behaviors
B. Offloading most optimizations to hardware microcode
C. Avoiding register allocation tasks entirely
D. Only producing microcoded sequences
Answer: A. Relying heavily on compiler to combine simple instructions into complex behaviors

63. In a register-memory machine (a hybrid), an operation like ADD A, R can mean:
A. Add register R to memory location A and store result in memory A
B. Add only immediate zero
C. Add and always use stack only
D. Only modify floating point units
Answer: A. Add register R to memory location A and store result in memory A

64. Which addressing mode is likely to be the fastest in hardware access time?
A. Immediate and register direct addressing (since no memory access required)
B. Multi-level indirect addressing always
C. Indexed with large page faults always
D. PC-relative with full-page table walk every time
Answer: A. Immediate and register direct addressing (since no memory access required)

65. What does the effective address mean?
A. The logical register ID used for decoding only
B. The final computed memory address that will be used to access data
C. The address of the next instruction always
D. An address stored in cache never in RAM
Answer: B. The final computed memory address that will be used to access data

66. An instruction that both loads from memory and performs arithmetic in one complex instruction reflects which ISA style?
A. RISC style load/store architecture
B. CISC style memory-to-memory or register-memory instructions
C. Pure stack-only ISA exclusively
D. VLIW exclusively
Answer: B. CISC style memory-to-memory or register-memory instructions

67. In RISC, why are load and store instructions separated from arithmetic instructions?
A. To make arithmetic dependent on microcode only
B. To simplify instruction execution and ease pipelining
C. To force every program to be larger
D. To eliminate registers entirely
Answer: B. To simplify instruction execution and ease pipelining

68. Which addressing mode helps implement nested data structures easily by following pointers?
A. Immediate addressing only
B. Indirect addressing (register or memory indirect)
C. Relative addressing used for loops only
D. Immediate with large constants always
Answer: B. Indirect addressing (register or memory indirect)

69. Which instruction format field is essential for supporting different operand sizes (byte, word, double)?
A. Opcode must encode operand-size or a size specifier field must exist
B. Program Counter always stores operand size
C. Stack Pointer encodes operand size always
D. Cache line number holds operand-size info only
Answer: A. Opcode must encode operand-size or a size specifier field must exist

70. Which of the following is true about addressing modes and compiler design?
A. More addressing modes always simplify compiler design
B. More addressing modes can complicate code generation but may reduce code size
C. Compilers never make use of addressing modes
D. Addressing modes only affect linker, not compiler
Answer: B. More addressing modes can complicate code generation but may reduce code size

71. Which of these is a typical reason to use stack organization for expression evaluation in a compiler back-end?
A. Minimizes register pressure and yields straightforward code generation for postfix evaluation
B. Maximizes random access to registers always
C. Eliminates the need for memory management entirely
D. Guarantees fewer instructions than register use always
Answer: A. Minimizes register pressure and yields straightforward code generation for postfix evaluation

72. Which addressing mode requires the ALU to perform addition of register and immediate offset during effective address calculation?
A. Absolute addressing only
B. Base-plus-offset (displacement) addressing
C. Immediate addressing only
D. Register direct without offsets
Answer: B. Base-plus-offset (displacement) addressing

73. A machine that supports complex addressing modes such as scaled-index with displacement is most likely trying to optimize for:
A. Compact code for array indexing and addressing complex data structures
B. Faster immediate-only operations exclusively
C. Reducing number of pipeline stages always
D. Minimizing instruction length only
Answer: A. Compact code for array indexing and addressing complex data structures

74. Which of the following is typical of CISC instruction fetch and decode compared to RISC?
A. Simpler and always one cycle
B. More complex due to variable length and diverse operand encodings
C. Identical in complexity to RISC always
D. Performed by compiler at runtime only
Answer: B. More complex due to variable length and diverse operand encodings

75. Which architecture style tends to have a higher number of instructions implemented as single hardware-level micro-ops?
A. RISC tends to map instructions to a small number of simple micro-ops
B. CISC always maps each instruction to thousands of micro-ops only
C. Stack machines never use micro-ops
D. GPUs only use micro-ops, CPUs never do
Answer: A. RISC tends to map instructions to a small number of simple micro-ops

76. Which addressing mode is appropriate when an instruction should refer to location at (base + index × scale + displacement)?
A. Scaled-index addressing (complex addressing)
B. Immediate addressing only
C. Register direct with no arithmetic
D. PC-relative addressing without index
Answer: A. Scaled-index addressing (complex addressing)

77. In RISC instruction formats, a small immediate field is often sign-extended to:
A. Prevent arithmetic operations entirely
B. Match operand size for ALU and extended as needed at execution
C. Always produce zero only
D. Replace the PC always
Answer: B. Match operand size for ALU and extended as needed at execution

78. Which of the following best describes the “orthogonality” of an instruction set?
A. Having many specialized registers only for I/O
B. Any instruction can use any addressing mode or register, making the set regular and combinable
C. Using stack-based only operations
D. Inability to combine addressing modes with instructions
Answer: B. Any instruction can use any addressing mode or register, making the set regular and combinable

79. An instruction that updates the condition flags automatically after execution is more common in:
A. Many RISC designs (some reserve explicit instructions) and CISC designs both — but commonly available in CISC historically
B. Only in stack machines never in register machines
C. Only in GPUs exclusively
D. In no architectures ever
Answer: A. Many RISC designs (some reserve explicit instructions) and CISC designs both — but commonly available in CISC historically

80. Which organization uses fewer registers but relies on memory and stack for intermediate values?
A. General-purpose-register (register-file driven) organization
B. Stack organization (stack machines)
C. Register-windowed RISC exclusively
D. Vector register banks only
Answer: B. Stack organization (stack machines)

81. Which of the following addressing modes can be used to access fields inside a structure easily when base points to structure start?
A. Immediate addressing only
B. Base + displacement (field offset) addressing
C. PC-relative addressing only for code
D. Auto-decrement addressing only
Answer: B. Base + displacement (field offset) addressing

82. In register file design, increasing the number of registers may cause which hardware cost?
A. Reduced decoding complexity always
B. Larger register file area and potentially longer register read/write times
C. No changes in physical area or timing ever
D. Removal of pipeline hazards automatically
Answer: B. Larger register file area and potentially longer register read/write times

83. Which addressing mode would a compiler use for accessing function local variables on the stack?
A. Global absolute addressing only
B. Base (frame pointer) + offset addressing
C. PC-relative addressing always
D. Register indirect with kernel privileges only
Answer: B. Base (frame pointer) + offset addressing

84. Which technique reduces the need for complex addressing modes in hardware?
A. Moving complexity into compiler-generated sequences and simpler load/store primitives (RISC approach)
B. Adding more microcode in every instruction always
C. Using stack-only execution only
D. Removing registers entirely from design
Answer: A. Moving complexity into compiler-generated sequences and simpler load/store primitives (RISC approach)

85. In stacked-based ISAs, which of the following is often true about instruction operands?
A. Explicit register specifiers are always present for operands
B. Operands are implicitly the top elements of the stack, reducing operand-specifier bits
C. Only immediate addressing is supported
D. All instructions are variable-length microcoded sequences
Answer: B. Operands are implicitly the top elements of the stack, reducing operand-specifier bits

86. Which addressing mode would create greatest code portability across different load addresses when used for branch targets?
A. Absolute addressing with fixed memory addresses
B. PC-relative addressing (position-independent code)
C. Register direct to SP only
D. Auto-increment addressing with fixed offsets only
Answer: B. PC-relative addressing (position-independent code)

87. Which of the following best describes variable-length instruction formats in CISC?
A. Every instruction is exactly 16 bytes long always
B. Instructions can be one to many bytes with complex decoding rules
C. They prohibit immediate operands always
D. They only exist in RISC processors exclusively
Answer: B. Instructions can be one to many bytes with complex decoding rules

88. If an instruction set is orthogonal, a compiler can:
A. Use any register or addressing mode with any instruction, simplifying code generation
B. Cannot combine registers with addressing modes at all
C. Must always use the stack for temporary values only
D. Is forced to write microcode for each instruction always
Answer: A. Use any register or addressing mode with any instruction, simplifying code generation

89. Which of the following is a microarchitectural technique used to accelerate complex CISC instructions on modern CPUs?
A. Direct execution of every CISC instruction in single cycle always
B. Translating CISC instructions into simpler internal RISC-like micro-ops and executing them in an internal pipeline
C. Removing the cache entirely and using only registers
D. Making compilers ignore instruction set entirely
Answer: B. Translating CISC instructions into simpler internal RISC-like micro-ops and executing them in an internal pipeline

90. Which addressing mode is particularly useful for iterating through arrays with constant-sized elements?
A. Scaled-index addressing (index × element_size + base)
B. Immediate addressing only
C. PC-relative addressing only for code
D. Register direct without calculation
Answer: A. Scaled-index addressing (index × element_size + base)

91. Which instruction format detail is most important to keep fixed size for simplifying pipelining?
A. Having a fixed opcode width and total instruction length
B. Using variable encoding for every operand for flexibility only
C. Embedding microcode in every instruction word
D. Allowing instructions larger than cache line always
Answer: A. Having a fixed opcode width and total instruction length

92. Which of the following describes the main role of the register file in CPU microarchitecture?
A. To hold only flags and control signals
B. To provide fast, low-latency storage of operands and results for the ALU stages
C. To store all program code permanently
D. To replace main memory entirely
Answer: B. To provide fast, low-latency storage of operands and results for the ALU stages

93. Which addressing mode is commonly used for position-independent code (PIC) and shared libraries?
A. Absolute addressing with fixed addresses
B. PC-relative addressing for data and branches
C. Auto-decrement addressing only
D. Register direct only for global variables
Answer: B. PC-relative addressing for data and branches

94. Which of the following best summarizes the load/store restriction of RISC?
A. Only load and store instructions access memory; arithmetic uses registers only
B. All instructions can read and write memory freely in any combination
C. RISC forbids memory usage entirely
D. RISC requires memory operands for every instruction always
Answer: A. Only load and store instructions access memory; arithmetic uses registers only

95. Which addressing mode can be used to quickly implement stack pushing of function parameters?
A. Auto-decrement on SP (push) or auto-increment on SP (pop) addressing
B. PC-relative addressing only
C. Register direct with immediate always
D. Absolute addressing into code segment only
Answer: A. Auto-decrement on SP (push) or auto-increment on SP (pop) addressing

96. Which of the following is a reason modern CISC CPUs internally use RISC-like micro-ops?
A. To make decoding impossible
B. To enable deep pipelining and out-of-order execution for performance while retaining CISC compatibility
C. To guarantee no instruction ever accesses memory
D. To reduce clock frequency by half always
Answer: B. To enable deep pipelining and out-of-order execution for performance while retaining CISC compatibility

97. Which instruction format is best for compact code when many small immediates are used but pipeline simplicity is also desired?
A. Fixed-length format with a limited-size immediate field and separate load-immediate instruction for large constants
B. Only variable-length complex formats always
C. No instruction formats at all
D. Microcode-only format embedded in main memory always
Answer: A. Fixed-length format with a limited-size immediate field and separate load-immediate instruction for large constants

98. Which addressing mode is most likely to cause additional pipeline stalls due to complex calculation and multiple memory accesses?
A. Immediate addressing always
B. Multiple-level indirect addressing and scaled-index with complex displacement and page faults
C. Register direct with no calculation
D. PC-relative with small displacement only
Answer: B. Multiple-level indirect addressing and scaled-index with complex displacement and page faults

99. Which of these describes a benefit of three-address instruction formats in a general register machine?
A. They reduce the number of instructions required by avoiding extra moves to preserve sources
B. They always increase memory accesses compared to two-address formats
C. They are only used by stack machines
D. They require microcode for each instruction always
Answer: A. They reduce the number of instructions required by avoiding extra moves to preserve sources

100. For compiler-generated code on a register-rich RISC architecture, which is most beneficial?
A. Aggressive register allocation and minimizing loads/stores
B. Relying on auto-increment addressing to store everything on stack only
C. Using CISC complex instructions to reduce number of instructions exclusively
D. Never using immediate values
Answer: A. Aggressive register allocation and minimizing loads/stores