Basic Computer Organization and Design MCQ Questions and Answers
1. Who proposed the concept of stored program computer?
A. Alan Turing
B. Charles Babbage
C. John von Neumann
D. Konrad Zuse
2. In stored program architecture, instructions and data are stored in:
A. Registers
B. Cache
C. Main memory
D. ALU
3. The main advantage of stored program computers is:
A. Faster ALU
B. Reduced instruction length
C. Flexibility to modify programs without changing hardware
D. Lower cost
4. Which of the following is an example of instruction code?
A. ASCII
B. Machine language
C. Unicode
D. JPEG
5. An opcode in an instruction specifies:
A. Operand address
B. Data type
C. Operation to be performed
D. Instruction length
6. Addressing mode determines:
A. Size of instruction
B. How operand is accessed
C. Clock speed
D. Number of registers
7. Immediate addressing uses:
A. Memory address
B. Constant value inside instruction
C. Register content
D. I/O port
8. Which stored program computer architecture is widely used?
A. Harvard
B. Von Neumann
C. Von Neumann
D. Turing Machine
9. Instruction set architecture (ISA) is defined as:
A. Hardware design
B. Programmer-visible instructions
C. Control unit design
D. Memory organization
10. Machine instructions are generally classified into:
A. Arithmetic, Logical, Data Transfer, Control
B. Compiler, Interpreter, Assembler, Loader
C. High-level, Low-level, Assembly, Binary
D. Input, Output, Storage, Processing
11. The length of instructions in a typical stored program computer is:
A. Fixed
B. Variable
C. Either fixed or variable depending on the system
D. Unlimited
12. In a stored program, which memory stores both instructions and data?
A. ROM only
B. Cache only
C. RAM
D. Registers
13. Opcode is represented in:
A. Binary
B. Decimal
C. Hexadecimal
D. Octal
14. Microprogramming is mainly used for:
A. High-level programming
B. Implementing control unit logic
C. Memory management
D. Cache optimization
15. Which of the following best defines a program counter (PC)?
A. Stores ALU results
B. Holds input data
C. Holds address of next instruction
D. Stores flags
16. Which register holds the current instruction being executed?
A. Accumulator
B. MAR
C. Instruction Register (IR)
D. Program Counter
17. Memory Address Register (MAR) stores:
A. Instruction
B. Address of memory to be accessed
C. ALU result
D. Flag status
18. Accumulator (AC) is used for:
A. Intermediate arithmetic and logic operations
B. Instruction fetch
C. Program counter storage
D. Input-output buffering
19. Which register stores data temporarily for memory operations?
A. PC
B. Memory Buffer Register (MBR)
C. IR
D. AC
20. General-purpose registers are used for:
A. Only arithmetic
B. Only logic
C. Arithmetic, logic, and data transfer
D. Only input-output
21. Status registers are also called:
A. Control registers
B. Flag registers
C. Address registers
D. Data registers
22. Which register counts memory addresses sequentially?
A. MAR
B. Program Counter (PC)
C. IR
D. AC
23. Stack pointer (SP) holds:
A. Next instruction
B. Top of the stack
C. Data for ALU
D. Instruction opcode
24. Index registers are primarily used for:
A. Arithmetic operations
B. Modifying operand addresses during program execution
C. Input-output control
D. Interrupt handling
25. Floating-point registers store:
A. Integers
B. Characters
C. Floating-point numbers
D. Boolean values
26. Which register is used for indirect addressing?
A. AC
B. IR
C. Index or pointer register
D. PC
27. Data registers temporarily hold:
A. Addresses only
B. Flags
C. Data for processing
D. Instructions
28. Instruction Register (IR) is part of:
A. ALU
B. Memory
C. Control unit
D. Input-output unit
29. General-purpose registers are mainly located in:
A. RAM
B. CPU
C. ROM
D. Cache
30. Flag register contains:
A. Instruction set
B. Operand
C. Status of CPU operations (Zero, Carry, etc.)
D. Memory address
31. Machine instructions consist of:
A. ALU, Register, Memory
B. Opcode and operand(s)
C. Data and flag
D. Address and pointer
32. Which instruction type is used to move data from memory to register?
A. Arithmetic
B. Logical
C. Data transfer
D. Control
33. An unconditional branch instruction:
A. Executes conditionally
B. Executes arithmetic
C. Always changes program sequence
D. Accesses I/O
34. Instruction that performs addition is an example of:
A. Data transfer
B. Branch
C. Arithmetic
D. Input-output
35. Subroutine call instruction is classified as:
A. Arithmetic
B. Logical
C. Control
D. I/O
36. Zero-address instructions are typically used in:
A. Stack-based machines
B. Register machines
C. Memory-mapped machines
D. Harvard architecture
37. One-address instructions use:
A. Two operands in memory
B. One operand in memory, one implicit in AC
C. Only registers
D. Only stack
38. Two-address instructions specify:
A. Two operands, one may be destination
B. One operand
C. Three operands
D. Stack top only
39. Three-address instructions are efficient because:
A. Less memory used
B. Allow direct operation on three operands
C. Only AC used
D. No opcode needed
40. Immediate instructions include:
A. Memory address
B. Constant operand in instruction
C. Input device address
D. Flag register
41. Which instruction type manipulates bits directly?
A. Arithmetic
B. Logical
C. Control
D. Transfer
42. Control instructions include:
A. ADD, SUB
B. AND, OR
C. JMP, CALL, RET
D. LOAD, STORE
43. Machine instructions are executed in:
A. Seconds
B. Clock cycles
C. Minutes
D. Milliseconds
44. Instruction formats may include:
A. Register, Operand, Flag
B. Opcode, Address field(s), Mode
C. Program, Data, ALU
D. Stack, Heap, Cache
45. Which instruction type is essential for loops?
A. Arithmetic
B. Logical
C. Control (branching)
D. Input-output
46. Timing in a CPU refers to:
A. Instruction length
B. Clock speed only
C. Synchronization of operations in CPU
D. Cache access time
47. Control signals are used to:
A. Store data
B. Perform arithmetic
C. Manage data flow between CPU and memory or I/O
D. Access stack
48. Hardwired control unit uses:
A. Microprograms
B. Combinational logic circuits
C. ROM
D. RAM
49. Microprogrammed control unit stores control signals in:
A. RAM
B. Control memory (ROM/PLA)
C. Registers
D. Stack
50. Timing signals are generated by:
A. ALU
B. Registers
C. Clock
D. Instruction Register
51. Control word consists of:
A. Memory address
B. Opcode
C. Signals controlling CPU and peripherals
D. Program counter value
52. Sequence of control signals required to execute instruction is called:
A. Opcode
B. Instruction set
C. Microinstruction sequence
D. Timing chart
53. Synchronous CPU timing uses:
A. Event signals
B. Clock pulses
C. Asynchronous signals
D. Interrupt signals
54. Asynchronous timing is controlled by:
A. Clock
B. Event completion
C. Program counter
D. ALU output
55. Control signals can be:
A. Input-output only
B. Synchronous or asynchronous
C. Arithmetic only
D. Memory-only
56. Pulse signals for read/write operations are part of:
A. Registers
B. ALU
C. Timing and control
D. Stack
57. A control unit that can be easily modified is:
A. Hardwired
B. Microprogrammed
C. Stack-based
D. Register-only
58. Timing diagrams show:
A. Instruction length
B. Sequence of signals and operations over time
C. Memory content
D. Register values
59. Which of the following is faster in execution?
A. Microprogrammed control
B. Hardwired control
C. Both same
D. Depends on memory
60. Control unit generates signals to:
A. Access compiler
B. Optimize code
C. Direct CPU, memory, and I/O operations
D. Increase cache size
61. Instruction cycle is also called:
A. Microcycle
B. Fetch-Execute cycle
C. Opcode cycle
D. Memory cycle
62. First step of instruction cycle is:
A. Execute
B. Decode
C. Fetch instruction from memory
D. Store result
63. Instruction cycle consists of:
A. Fetch, Execute
B. Fetch, Decode, Execute, Store
C. Fetch, Decode, Execute (optional Store)
D. Fetch, Store
64. Decode step converts instruction into:
A. Data
B. Control signals
C. Memory address
D. Register value
65. Execute step involves:
A. Fetching instruction
B. Performing operation specified by instruction
C. Generating opcode
D. Accessing stack
66. Memory-reference instructions require:
A. Registers only
B. ALU only
C. Memory access
D. Control unit only
67. Input-output instructions usually use:
A. ALU only
B. Memory only
C. I/O devices
D. Registers only
68. Instruction cycle time depends on:
A. Compiler efficiency
B. Clock speed and memory access time
C. Instruction length only
D. ALU design only
69. Which of the following is part of instruction cycle?
A. Clock generation
B. Instruction fetch, decode, execute
C. Stack management
D. Cache mapping
70. Instruction cycle count can be reduced by:
A. Using larger memory
B. Pipelining
C. Increasing registers
D. Decreasing opcode
71. During fetch, the instruction is stored in:
A. AC
B. IR
C. PC
D. MAR
72. Instruction cycle repeats for:
A. One instruction only
B. One program
C. All instructions in program
D. ALU operations only
73. Execution time of instruction includes:
A. Decode only
B. Fetch + Decode + Execute
C. Fetch only
D. Control signals only
74. Instruction cycle can be measured in:
A. Seconds only
B. Clock cycles
C. Instructions
D. Registers
75. Multi-cycle instruction execution is used to:
A. Simplify opcode
B. Reduce average cycle time
C. Increase instruction length
D. Avoid branching
76. Memory-reference instructions access:
A. Registers only
B. Main memory
C. I/O devices
D. Cache only
77. Load instruction is used to:
A. Store data
B. Transfer data from memory to register
C. Perform addition
D. Jump instruction
78. Store instruction:
A. Transfers data from register to memory
B. Reads input
C. Performs ALU operations
D. Modifies PC
79. Direct addressing specifies:
A. Operand in AC
B. Immediate data
C. Exact memory address of operand
D. Stack location
80. Indirect addressing uses:
A. Memory address stored in a register or memory
B. Constant value
C. Input device
D. Opcode field
81. Register addressing stores operand in:
A. Memory
B. CPU register
C. Stack
D. Control unit
82. Effective address in memory-reference instructions:
A. Is opcode
B. Is immediate data
C. Final address where operand resides
D. Register value
83. Memory-reference instructions are mostly executed by:
A. Input-output devices
B. ALU with memory access
C. Registers only
D. Control unit only
84. Addressing mode determines:
A. Clock speed
B. How operand is accessed
C. Opcode length
D. Instruction cycle
85. Which instruction transfers multiple bytes from memory to register?
A. Jump
B. Block transfer
C. ALU operation
D. Interrupt
86. Input-output instructions allow CPU to:
A. Perform arithmetic
B. Store data only
C. Communicate with external devices
D. Decode instructions
87. Programmed I/O requires:
A. Hardware interrupts
B. CPU actively waits for I/O completion
C. DMA
D. Cache only
88. Direct Memory Access (DMA) allows:
A. CPU to control all I/O
B. Data transfer between memory and I/O without CPU
C. Only registers access
D. ALU-only operations
89. Input devices provide:
A. Control signals
B. Data to CPU
C. Memory addresses
D. Opcodes
90. Output devices receive:
A. Instructions
B. Processed data from CPU
C. Operand only
D. Memory addresses
91. I/O mapped in memory uses:
A. Same address space as memory
B. Separate address space
C. Registers
D. Cache
92. Interrupt-driven I/O:
A. CPU waits actively
B. CPU executes other instructions until I/O signals completion
C. Only used in DMA
D. Uses no control signals
93. Status register for I/O devices indicates:
A. Memory address
B. Ready, busy, or error state
C. Instruction code
D. ALU result
94. Which type of I/O uses polling?
A. DMA
B. Programmed I/O
C. Interrupt-driven
D. None
95. Bus arbitration is required when:
A. Only one device exists
B. Multiple devices share system bus
C. Registers are empty
D. Stack is full
96. An interrupt is:
A. ALU operation
B. Signal to CPU to temporarily halt current execution
C. Memory access
D. Input signal only
97. Hardware interrupts are generated by:
A. I/O devices or timers
B. Compiler
C. Stack overflow
D. Registers
98. Software interrupt is caused by:
A. Device request
B. Instruction in program
C. ALU operation
D. Cache access
99. Interrupt vector contains:
A. Opcode
B. Address of interrupt service routine (ISR)
C. Data to ALU
D. Memory address only
100. After servicing an interrupt, CPU resumes:
A. Next program only
B. Execution from where it was interrupted
C. Restart program
D. Fetch next instruction only