Register Transfer and Microoperations MCQ Questions and Answers
1. The notation R2 ← R1 in RTL represents:
A) Data moves from R2 to R1
B) Data moves from R1 to R2
C) R1 and R2 are swapped
D) R1 is cleared after transfer
2. The control function in RTL is used to:
A) Identify bus direction
B) Specify hardware implementation
C) Indicate when a transfer should occur
D) Determine opcode format
3. A register transfer operation can occur only when:
A) CPU is idle
B) Register is full
C) The control condition is true
D) Memory is enabled
4. Which symbol is used in RTL to denote conditional transfer?
A) ↑
B) If (P):
C) ←
D) ↔
5. The statement P: R2 ← R1 means:
A) Transfer R1 to R2 only if P=1
B) Always transfer R1 to R2
C) Transfer R2 to R1 if P=1
D) P represents a register
6. RTL is mainly used to:
A) Optimize code
B) Describe data flow between registers
C) Represent assembly instructions
D) Execute ALU operations
7. The width of a register refers to:
A) Number of microoperations it performs
B) Number of bits it can store
C) Number of buses connected
D) Clock cycles per transfer
8. The control signals in RTL are generated by:
A) Bus controller
B) ALU
C) Control unit
D) Decoder
9. The RTL description R3 ← R1 + R2 involves:
A) An arithmetic microoperation
B) A shift microoperation
C) A logic microoperation
D) A memory transfer
10. In RTL, the arrow symbol ← indicates:
A) Addition
B) Comparison
C) Assignment/transfer
D) Multiplication
11. A bus in computer architecture is:
A) A register
B) A storage device
C) A set of shared communication lines
D) An instruction decoder
12. The function of a bus system is to:
A) Execute arithmetic operations
B) Manage cache memory
C) Transfer data between components
D) Generate control signals
13. A tri-state buffer is used in bus systems to:
A) Control data flow direction
B) Increase register capacity
C) Perform logical AND
D) Reduce memory size
14. Bus contention occurs when:
A) Bus is idle
B) Two devices attempt to use the bus simultaneously
C) Bus lines are damaged
D) Control unit is disabled
15. Memory read operation involves:
A) Writing data to memory
B) Transferring data from memory to CPU
C) Clearing memory
D) Incrementing address
16. Memory write operation in RTL can be represented as:
A) M[AR] ← R1
B) R1 ← M[AR]
C) AR ← M[R1]
D) R1 + M[AR]
17. Bus multiplexing is used to:
A) Share same lines for address and data
B) Increase transfer speed
C) Perform addition faster
D) Reduce control signals
18. The number of lines in an n-bit bus is:
A) n/2
B) n²
C) n
D) 2n
19. A 16-bit bus can transfer:
A) 2 bytes
B) 2 bytes simultaneously
C) 4 bytes
D) 8 bytes
20. A multiplexer in bus design helps to:
A) Decode instructions
B) Select one data source among many
C) Generate timing pulses
D) Store control words
21. The microoperation R3 ← R1 + R2 performs:
A) Shift operation
B) Addition
C) Subtraction
D) Logic AND
22. Arithmetic microoperations perform:
A) Comparison
B) Data transfer
C) Basic arithmetic computations
D) Logical operations
23. The operation R2 ← R2 + 1 represents:
A) Shift left
B) Logical OR
C) Increment operation
D) Complement
24. Subtraction is usually performed by:
A) Adding the 2’s complement
B) Direct subtraction circuit
C) Multiplexing
D) Exclusive-OR
25. Overflow occurs when:
A) All bits are zero
B) Result exceeds the representable range
C) Registers are swapped
D) Bus lines are shorted
26. Arithmetic microoperations are executed in:
A) Memory unit
B) ALU
C) Control unit
D) Decoder
27. The operation R1 ← R1 – R2 can also be expressed as:
A) R1 ← R2 + R1
B) R1 ← R1 XOR R2
C) R1 ← R1 + (2’s complement of R2)
D) R1 ← NOT R2
28. Increment operation requires:
A) A subtractor
B) A binary adder with one input fixed at 1
C) Shift circuit
D) Decoder
29. In binary arithmetic, carry generation happens when:
A) Both bits are 0
B) One bit is 1
C) Both bits are 1
D) Carry input is zero
30. The operation R ← R + R is equivalent to:
A) Complement
B) Shift left by one bit
C) Shift right
D) Logical OR
31. Logic microoperations operate on:
A) Individual bits of data
B) Floating point numbers
C) Memory addresses only
D) Instruction codes
32. The microoperation R1 ← R1 AND R2 performs:
A) OR
B) XOR
C) Bitwise AND
D) Complement
33. The complement operation can be written as:
A) R ← R
B) R ← R + 1
C) R ← R / 2
D) R ← R + R
34. Which of the following is a logical operation?
A) Subtract
B) XOR
C) Add
D) Multiply
35. The logic operation R1 ← R1 OR R2 results in:
A) Bitwise union of bits
B) Bitwise intersection
C) Shifted bits
D) Arithmetic carry
36. A logic microoperation used to compare equality is:
A) OR
B) ADD
C) XNOR
D) AND
37. The operation R ← 0 is called:
A) Complement
B) Clear operation
C) Set operation
D) Decrement
38. Logic microoperations are implemented using:
A) Logic gates
B) Multiplexers only
C) Shift registers
D) Memory array
39. The Exclusive OR (XOR) operation gives output 1 when:
A) Both inputs are same
B) Inputs are different
C) Both inputs are 1
D) Both inputs are 0
40. The Set operation makes all bits of register:
A) 0
B) 1
C) Random
D) Complemented
41. A shift microoperation moves bits:
A) Randomly
B) Left or right within a register
C) Between registers
D) From bus to memory
42. Logical shift differs from arithmetic shift because:
A) It does not preserve sign bit
B) It adds 1 to the MSB
C) It performs rotation
D) It doubles the number
43. Arithmetic right shift preserves:
A) Sign bit (MSB)
B) LSB
C) Carry flag
D) Overflow bit
44. The operation R ← shl R means:
A) Shift left
B) Shift right
C) Rotate left
D) Complement bits
45. A rotate left operation differs from shift left in that:
A) Bits are lost
B) MSB is circulated to LSB
C) All bits become zero
D) Carry bit is ignored
46. The shift operation that discards bits shifted out is:
A) Rotate
B) Logical shift
C) Arithmetic shift
D) Complement
47. If a register initially has 1010 and we apply a logical right shift, the result is:
A) 0101
B) 1101
C) 1110
D) 1001
48. Shift operations are used in:
A) Input/Output control
B) Multiplication and division by 2
C) Logical comparison
D) Interrupt handling
49. In an arithmetic left shift, the sign bit:
A) Is preserved
B) May change, indicating overflow
C) Is complemented
D) Remains zero
50. The rotate right operation on 1001 gives:
A) 0011
B) 1100
C) 0110
D) 0100
51. Which microoperation type performs bit manipulation?
A) Arithmetic
B) Logic
C) Control
D) Memory
52. A microoperation that combines shift and addition is:
A) Arithmetic shift
B) Logical shift
C) Rotate
D) Complement
53. Which unit executes all microoperations?
A) Memory
B) ALU
C) Control unit
D) Decoder
54. The notation R1 ← R1 + 1 represents:
A) Decrement
B) Increment
C) Complement
D) Rotate
55. The hardware required for shift microoperations is:
A) Decoder
B) Shift register
C) Multiplexer
D) Counter
56. The result of logical AND between 1010 and 1100 is:
A) 1110
B) 1000
C) 0100
D) 1011
57. The result of logical OR between 1010 and 0101 is:
A) 0000
B) 1111
C) 1010
D) 0101
58. XOR is often used for:
A) Bitwise comparison and parity checking
B) Data transfer
C) Increment
D) Division
59. The bus system allows:
A) Multiple components to share communication lines
B) Only memory to CPU transfer
C) Only register to register data flow
D) Only ALU operations
60. The number of control lines required for an 8-to-1 multiplexer is:
A) 2
B) 4
C) 3
D) 5
61. In a CPU, the address bus is:
A) Bidirectional
B) Unidirectional (from CPU to memory)
C) Bidirectional (from memory to CPU)
D) Random access
62. The data bus typically:
A) Transfers only instructions
B) Transfers both data and instructions
C) Transfers addresses only
D) Stores opcodes permanently
63. Control bus lines include:
A) Address bits only
B) Signals for read, write, and interrupt
C) Data bits only
D) Clock pulse lines
64. During a memory read, the CPU:
A) Places the address on the address bus and reads data from memory
B) Sends data to memory
C) Clears the accumulator
D) Changes the program counter
65. During a memory write, the CPU:
A) Fetches instruction
B) Reads data from memory
C) Sends data to memory using data bus
D) Performs a logic operation
66. A bus arbiter is responsible for:
A) Arithmetic computation
B) Granting bus access to one device at a time
C) Error correction
D) Parity generation
67. When two registers are connected to a common bus, each uses:
A) Decoder
B) Tri-state buffer or multiplexer
C) Counter
D) Shifter
68. A register transfer can be synchronous or asynchronous depending on:
A) Address width
B) Clock control
C) Bus lines
D) Data type
69. The memory address register (MAR) holds:
A) Instruction code
B) Data value
C) Address of memory location to be accessed
D) Control signal
70. The memory data register (MDR) holds:
A) Address
B) Opcode
C) Data being transferred to/from memory
D) Instruction counter
71. The operation R ← R – 1 is called:
A) Increment
B) Decrement
C) Complement
D) Rotate
72. In binary addition, the half adder generates:
A) Sum and Carry
B) Only Sum
C) Only Carry
D) Overflow
73. The full adder differs from half adder by:
A) Number of inputs
B) Inclusion of carry input
C) Absence of sum output
D) Having more outputs
74. Subtraction A – B can be done using:
A) A + B
B) A + (2’s complement of B)
C) A – (2’s complement of A)
D) A XOR B
75. Overflow can only occur when:
A) Adding two numbers of the same sign
B) Adding numbers of opposite sign
C) Performing logical AND
D) Shifting bits
76. In an 8-bit signed system, adding 01111111 + 00000001 results in:
A) Overflow
B) Zero
C) Negative number
D) Logical shift
77. The complement of 1010 is:
A) 0101
B) 1010
C) 1111
D) 0010
78. The arithmetic unit can perform subtraction without a subtractor using:
A) Exclusive OR
B) Adder and complement logic
C) Shift register
D) Decoder
79. The carry-out bit from MSB in addition is used to:
A) Check parity
B) Detect overflow in unsigned operations
C) Perform XOR
D) Indicate rotation
80. Arithmetic microoperations can include:
A) OR, XOR, NOT
B) AND, NAND
C) Add, Subtract, Increment, Decrement
D) Set, Clear
81. Bitwise complement changes:
A) Only MSB
B) Every bit from 0 to 1 and 1 to 0
C) Only least significant bit
D) None of these
82. The XOR operation acts as:
A) Binary difference (without borrow)
B) Logical AND
C) Parity inversion
D) Shift
83. The logical identity A XOR A = ? gives:
A) 0
B) 1
C) A
D) A’
84. Which operation is used to clear specific bits in a register?
A) OR with 1
B) AND with 0s
C) XOR with 1
D) Complement
85. The operation R ← R AND 0 results in:
A) Cleared register
B) All bits set
C) Complemented bits
D) Rotated bits
86. The OR operation is used to:
A) Set bits
B) Clear bits
C) Rotate bits
D) Complement bits
87. If A = 1010 and B = 1100, then A XOR B =
A) 1111
B) 0110
C) 1000
D) 1101
88. Which operation can be used to invert selected bits only?
A) AND
B) OR
C) XOR
D) ADD
89. The logical AND operation results in 1 only when:
A) Either bit is 1
B) Both bits are 0
C) Both bits are 1
D) One bit is 0
90. If a register is ANDed with itself, the output is:
A) All 1s
B) Same as input
C) All 0s
D) Complement
91. A shift left operation is equivalent to:
A) Multiplication by 2
B) Division by 2
C) Addition
D) Complement
92. A shift right operation is equivalent to:
A) Multiplication by 2
B) Division by 2 (for unsigned numbers)
C) Subtraction
D) XOR
93. Rotate operations are used to:
A) Complement bits
B) Circulate bits without loss
C) Clear register
D) Encode address
94. The logical left shift of 0011 gives:
A) 0110
B) 1100
C) 1000
D) 0001
95. The arithmetic right shift of 1110 gives:
A) 0111
B) 1111
C) 0001
D) 1011
96. In shift operations, the vacated bit position is usually filled with:
A) 0 or sign bit
B) Random value
C) Carry bit
D) Overflow flag
97. Circular shift differs from arithmetic shift because:
A) No bit is lost; bits are rotated
B) It uses sign extension
C) It clears register
D) It complements bits
98. For a 4-bit register 1101, rotate left gives:
A) 1011
B) 0110
C) 1110
D) 1001
99. Shift microoperations are often combined with:
A) Arithmetic operations for efficient multiplication/division
B) Logic operations only
C) Memory fetch
D) Address decoding
100. The hardware circuit used for performing shift microoperations is called:
A) Counter
B) Decoder
C) Shift Register
D) Adder