ALU, Data‐Path and Control Unit MCQ Questions and Answers in Computer Organization and Architecture
1. The ALU performs which of the following operations?
a) Only logical operations
b) Only arithmetic operations
c) Both arithmetic and logical operations
d) Memory management operations
2. In an ALU, the carry look-ahead adder improves performance by:
a) Reducing gate delay
b) Reducing carry propagation time
c) Increasing number of adders
d) Removing multiplexers
3. The overflow flag in an ALU is set when:
a) The sum is zero
b) The result exceeds the representable range
c) Carry is not generated
d) Sign bit is unchanged
4. A logical shift right operation on a binary number moves bits:
a) To the right and fills leftmost bit with 0
b) To the left and fills rightmost bit with 0
c) To the right and preserves sign
d) To the left and preserves sign
5. In a two’s complement ALU, subtraction is implemented using:
a) Exclusive OR gate
b) Multiplexer
c) Addition with complement and carry-in
d) NAND gate
6. Which of the following ALU components determines the result’s sign?
a) Most significant bit
b) Least significant bit
c) Overflow flag
d) Zero flag
7. The zero flag in an ALU indicates:
a) A negative result
b) Result of operation is zero
c) Result overflow
d) No carry generated
8. A ripple-carry adder is slower than a carry look-ahead adder because:
a) Carries propagate sequentially through stages
b) More hardware is used
c) It computes partial sums
d) Carries are generated in parallel
9. Logical AND operation in an ALU is equivalent to:
a) Multiplication of signed numbers
b) Bitwise multiplication
c) Subtraction of bits
d) Logical inversion
10. Which part of an ALU determines what operation to perform?
a) Control lines from the control unit
b) Memory address register
c) Instruction decoder
d) Program counter
11. The data path connects which main components?
a) Registers, ALU, and memory
b) Cache and CPU
c) I/O devices only
d) Only memory units
12. A single bus data path suffers from:
a) Bottleneck due to one transfer at a time
b) Multiple simultaneous transfers
c) Lack of synchronization
d) No control signal
13. In a two-bus data path, one bus is typically used for:
a) Instructions only
b) Source operands
c) Destination registers
d) Control signals
14. The role of multiplexers in a data path is to:
a) Store intermediate results
b) Select one input among many
c) Perform logic operations
d) Generate timing signals
15. The control signals in a data path determine:
a) Which memory to access
b) Which data flow path to activate
c) Clock frequency
d) Data encoding scheme
16. Pipelining in a data path increases:
a) Throughput
b) Latency
c) Clock period
d) Instruction fetch time
17. The Register File in a data path is used to:
a) Provide fast access to operands
b) Store programs permanently
c) Manage interrupts
d) Control branching
18. The temporary data storage between the ALU and main memory is:
a) Register file
b) Cache memory
c) Program counter
d) Decoder
19. A load instruction transfers data:
a) From memory to a register
b) From register to memory
c) Between registers
d) From I/O to ALU
20. In a datapath, the MAR holds:
a) Address of memory to be accessed
b) Result of computation
c) Instruction code
d) Operand value
21. The control unit generates:
a) Timing and control signals
b) Arithmetic results
c) I/O interrupts
d) Memory addresses
22. A hardwired control unit is:
a) Faster but less flexible
b) Slower but more flexible
c) Always microprogrammed
d) Implemented in software
23. A microprogrammed control unit uses:
a) Control memory to store microinstructions
b) Combinational circuits only
c) Multiplexers for timing
d) ALU for control
24. The main advantage of microprogrammed control is:
a) Easier to modify control logic
b) Lower hardware cost
c) Always faster
d) Simpler pipeline design
25. The control word in a microprogrammed unit specifies:
a) Control signals to activate data path elements
b) Machine instruction format
c) Address of next instruction
d) Operand location
26. A control store holds:
a) Microinstructions
b) Machine instructions
c) Interrupt vectors
d) Source code
27. The sequencing counter in a control unit is used to:
a) Point to the next microinstruction
b) Address main memory
c) Store operand values
d) Indicate instruction length
28. In a hardwired control, modifying an instruction set means:
a) Changing hardware connections
b) Changing control memory
c) Reloading firmware
d) Modifying ALU registers
29. The microinstruction format defines:
a) Fields for control signals and next address
b) Operand formats
c) Pipeline depth
d) Instruction set length
30. The control unit does not directly perform:
a) Arithmetic computations
b) Sequence generation
c) Signal activation
d) Timing control
31. The result of an ALU operation is stored in:
a) A register
b) Main memory directly
c) Control unit
d) Instruction queue
32. During instruction execution, the control unit:
a) Directs data movement through the data path
b) Performs logical comparisons
c) Stores intermediate results
d) Changes bus width
33. Which signal determines the ALU operation mode?
a) Operation select lines (OpCode)
b) Program counter
c) Memory read/write
d) Data register
34. When a branch instruction is executed, the data path updates:
a) Program counter
b) ALU accumulator
c) Memory buffer register
d) Control word
35. The link between the control unit and ALU is primarily through:
a) Control signals
b) Data buses only
c) Cache interface
d) I/O ports
36. The carry flag in an ALU is used to:
a) Detect sign changes
b) Indicate carry out from the most significant bit
c) Signal overflow in addition
d) Show zero result
37. Which ALU operation is commonly used in multiplication algorithms?
a) Shift and add
b) Logical OR
c) Rotate left
d) Masking
38. A barrel shifter in a processor is used for:
a) Shifting multiple bits in one clock cycle
b) Performing addition faster
c) Increasing bus width
d) Multiplying numbers
39. Saturation arithmetic is used in ALUs to:
a) Limit results to a fixed maximum/minimum range
b) Speed up multiplication
c) Avoid carry propagation
d) Eliminate sign bit
40. In a 32-bit ALU, how many result bits are generated by an addition?
a) 32 bits plus one carry bit
b) 33 bits always
c) Only 31 bits
d) Variable depending on operands
41. The function select lines of an ALU are used to:
a) Choose the specific operation to perform
b) Control memory timing
c) Manage clock cycles
d) Load new data into registers
42. Overflow does not occur in which of the following cases?
a) Addition of numbers with different signs
b) Addition of same sign numbers
c) Subtraction of same sign numbers
d) Signed multiplication
43. A half adder can perform:
a) Addition of two bits without carry input
b) Addition with carry propagation
c) Subtraction of bits
d) Logical operations only
44. The arithmetic shift differs from logical shift because:
a) It preserves the sign bit
b) It always shifts zeros in
c) It uses two control lines
d) It doubles the value
45. The “set on less than” operation in an ALU is useful for:
a) Conditional branching
b) Floating point division
c) Clock synchronization
d) Data encryption
46. In a CPU data path, the Instruction Register (IR) holds:
a) The current instruction being executed
b) The address of the next instruction
c) The result of the ALU
d) A constant operand
47. The bus width of the datapath determines:
a) Number of bits transferred per cycle
b) Size of control memory
c) Number of instructions in cache
d) Pipeline depth
48. The function of a tri-state buffer in a datapath is to:
a) Control access to a shared bus
b) Perform arithmetic operations
c) Store operands temporarily
d) Control instruction decoding
49. The Memory Buffer Register (MBR) acts as:
a) A temporary holding place for data from/to memory
b) A counter for memory access
c) A flag register
d) A microinstruction decoder
50. When an instruction fetch occurs, the data path typically:
a) Sends the PC value to the MAR
b) Loads the PC from memory
c) Writes data to ALU
d) Clears control signals
51. The main memory and CPU exchange data through:
a) Data bus
b) Address decoder
c) Control unit
d) Register file
52. A single-cycle datapath executes:
a) One instruction per clock cycle
b) Multiple instructions concurrently
c) Instructions over multiple stages
d) Several threads
53. A multi-cycle datapath divides execution into:
a) Fetch, decode, execute, memory, and write-back steps
b) One giant instruction per cycle
c) Random stages
d) Only arithmetic operations
54. Control signals for register file read and write are typically:
a) Generated by the control unit
b) Part of the ALU flags
c) Generated by the memory bus
d) Randomly generated each cycle
55. The purpose of a status register in the datapath is to:
a) Hold ALU condition codes
b) Store memory data
c) Track clock cycles
d) Save program instructions
56. The next microinstruction address in a microprogrammed control unit is obtained from:
a) Sequencer logic
b) ALU output
c) Instruction register
d) Data bus
57. Microoperations are defined as:
a) Basic operations executed on data path elements
b) Entire machine instructions
c) Program counter updates
d) Timing pulses
58. A control signal that enables writing to a register is:
a) Load enable
b) Clock enable
c) Read strobe
d) Data valid
59. In microprogrammed control, the microinstruction sequencing is controlled by:
a) Microprogram counter
b) ALU status bits
c) Memory address register
d) I/O interface
60. In horizontal microprogramming, control words are:
a) Wide and specify many signals explicitly
b) Compact and encoded
c) Sequentially stored in registers
d) Generated using multiplexers
61. The purpose of a microinstruction decoder is to:
a) Generate control signals from microinstruction fields
b) Execute arithmetic operations
c) Store microprogram addresses
d) Convert opcodes into machine code
62. Vertical microprogramming reduces:
a) Control word width
b) Control store access time
c) Number of microoperations
d) Clock frequency
63. The “Next Address Generator” in a control unit determines:
a) The address of the next microinstruction
b) The data value to be fetched
c) The pipeline stage to be executed
d) The memory control signal
64. A control word contains information to:
a) Activate control lines for one microoperation
b) Select input operands for the ALU
c) Store data in main memory
d) Schedule I/O devices
65. The microinstruction cycle typically includes:
a) Fetch, decode, and store
b) Fetch and execute of microinstructions
c) Arithmetic and logic execution
d) Branch prediction
66. The control store is implemented using:
a) ROM or PLA
b) Register file
c) SRAM cache
d) Flash memory
67. Microinstruction branching allows:
a) Conditional sequencing based on ALU flags
b) Reordering of machine instructions
c) Parallel data transfer
d) Clock adjustment
68. The width of a microinstruction depends mainly on:
a) Number of control signals
b) Size of main memory
c) Opcode length
d) Instruction fetch time
69. Which of the following is true for microprogrammed control?
a) It is easier to modify than hardwired control
b) It is always faster
c) It uses fewer signals
d) It eliminates need for ALU flags
70. The performance of a microprogrammed control unit can be improved by:
a) Using a cache for microinstructions
b) Reducing bus width
c) Disabling pipelining
d) Slowing the clock
71. Pipelining improves processor performance by:
a) Overlapping execution of instructions
b) Reducing instruction length
c) Increasing clock period
d) Removing branch operations
72. A structural hazard in a pipeline occurs when:
a) Two stages need the same hardware resource simultaneously
b) The wrong branch is taken
c) Instruction length is variable
d) ALU overflow occurs
73. Data hazard occurs due to:
a) Dependency between instructions
b) Memory failure
c) Cache misses
d) Control signal delay
74. Control hazards primarily arise from:
a) Branch instructions
b) Arithmetic overflow
c) Memory write conflicts
d) Cache coherence
75. Pipeline latency refers to:
a) Time between input and corresponding output
b) Number of instructions per second
c) Total pipeline stages
d) Instruction fetch speed
76. Instruction throughput is measured as:
a) Instructions completed per unit time
b) Time taken for one instruction
c) Size of instruction register
d) Frequency of interrupts
77. A pipeline stall is inserted to:
a) Resolve data or control hazards
b) Increase instruction speed
c) Optimize branch prediction
d) Reduce memory latency
78. Superscalar processors improve throughput by:
a) Issuing multiple instructions per cycle
b) Increasing clock speed only
c) Using one large ALU
d) Reducing control signals
79. Pipeline bubbles represent:
a) Empty stages waiting for data
b) Multiple operands in ALU
c) Extra control signals
d) Parity bits in data path
80. Branch prediction helps to:
a) Reduce pipeline stalls from conditional branches
b) Increase cache capacity
c) Modify control words dynamically
d) Eliminate arithmetic errors
81. In synchronous systems, all operations are coordinated by:
a) Clock signal
b) Control bus
c) Memory access pattern
d) Interrupt controller
82. The control unit uses a clock to:
a) Synchronize microoperations
b) Execute ALU computations
c) Store temporary data
d) Generate overflow flags
83. Skew in clock signals can cause:
a) Timing errors in data transfer
b) Reduced ALU precision
c) Larger instruction size
d) Excessive control signals
84. Asynchronous control units are characterized by:
a) Event-driven sequencing without a global clock
b) Strict cycle synchronization
c) Use of only flip-flops
d) High-speed pipelining
85. A hazard caused by slow propagation of control signals is a:
a) Timing hazard
b) Data hazard
c) Structural hazard
d) Branch hazard
86. The control unit coordinates ALU and memory operations through:
a) Control signals and timing pulses
b) Program counter updates only
c) Interrupt service routines
d) Data hazard elimination
87. The instruction cycle in a processor is managed primarily by:
a) Control unit sequencing
b) ALU flags
c) Memory hierarchy
d) System clock generator
88. During the “decode” phase, the control unit:
a) Interprets the opcode and generates control signals
b) Transfers data to the ALU
c) Stores results into memory
d) Clears flag registers
89. The program counter (PC) is incremented:
a) After fetching an instruction
b) During memory read operation
c) During ALU execution
d) After branch misprediction
90. In a typical data path, the accumulator is used to:
a) Hold intermediate ALU results
b) Store instruction opcodes
c) Manage I/O devices
d) Address cache memory
91. The control unit directs which register to write into by using:
a) Destination select signals
b) Data flags
c) MAR address lines
d) Branch control codes
92. The main purpose of control lines between ALU and control unit is to:
a) Indicate status and completion of operations
b) Send operand values
c) Fetch instruction bits
d) Store data in cache
93. A “control signal conflict” occurs when:
a) Two control lines activate conflicting operations
b) A register file overflows
c) Two ALUs share a bus
d) Branch prediction fails
94. In a CPU, instruction sequencing is maintained by:
a) Next address logic in the control unit
b) ALU status bits
c) Condition code registers
d) Cache controller
95. When an interrupt occurs, control is transferred to:
a) Interrupt Service Routine (ISR)
b) Data bus controller
c) Program counter directly
d) Memory buffer register
96. In RISC processors, the control unit is generally:
a) Hardwired for faster operation
b) Microprogrammed for flexibility
c) Implemented using firmware only
d) Always asynchronous
97. In CISC processors, the control unit is often:
a) Microprogrammed for complex instructions
b) Hardwired for simple decoding
c) Static without branching
d) Reduced to minimal logic
98. The datapath width of a processor affects:
a) The number of bits processed per cycle
b) The number of control signals
c) Cache associativity
d) Program counter depth
99. When multiple ALUs operate in parallel under one control unit, it is known as:
a) SIMD (Single Instruction Multiple Data)
b) MIMD (Multiple Instruction Multiple Data)**
c) SISD (Single Instruction Single Data)**
d) MISD (Multiple Instruction Single Data)**
100. The ultimate role of the datapath and control unit combination is to:
a) Execute instructions correctly and efficiently
b) Store programs permanently
c) Manage operating system functions
d) Provide network communication